eddsa.qsf

# -------------------------------------------------------------------------- #
#
# Copyright (C) 2022  Intel Corporation. All rights reserved.
# Your use of Intel Corporation's design tools, logic functions 
# and other software and tools, and any partner logic 
# functions, and any output files from any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Intel Program License 
# Subscription Agreement, the Intel Quartus Prime License Agreement,
# the Intel FPGA IP License Agreement, or other applicable license
# agreement, including, without limitation, that your use is for
# the sole purpose of programming logic devices manufactured by
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# https://fpgasoftware.intel.com/eula.
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# -------------------------------------------------------------------------- #
#
# Quartus Prime
# Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition
# Date created = 18:11:24  October 31, 2024
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
#		eddsa_assignment_defaults.qdf
#    If this file doesn't exist, see file:
#		assignment_defaults.qdf
#
# 2) Intel recommends that you do not modify this file. This
#    file is updated automatically by the Quartus Prime software
#    and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #


set_global_assignment -name FAMILY "Cyclone V"
set_global_assignment -name DEVICE 5CEBA4F23C7
set_global_assignment -name TOP_LEVEL_ENTITY add_8_parts
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 21.1.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "18:11:24  OCTOBER 31, 2024"
set_global_assignment -name LAST_QUARTUS_VERSION "21.1.1 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256
set_global_assignment -name EDA_SIMULATION_TOOL "Questa Intel FPGA (SystemVerilog)"
set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "SYSTEMVERILOG HDL" -section_id eda_simulation
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_timing
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_symbol
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_signal_integrity
set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_board_design_boundary_scan
set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
set_instance_assignment -name VIRTUAL_PIN ON -to a
set_instance_assignment -name VIRTUAL_PIN ON -to b
set_instance_assignment -name VIRTUAL_PIN ON -to sum
set_instance_assignment -name VIRTUAL_PIN ON -to result
set_instance_assignment -name VIRTUAL_PIN ON -to X2
set_instance_assignment -name VIRTUAL_PIN ON -to X3
set_instance_assignment -name VIRTUAL_PIN ON -to Y1
set_instance_assignment -name VIRTUAL_PIN ON -to Y2
set_instance_assignment -name VIRTUAL_PIN ON -to Y3
set_instance_assignment -name VIRTUAL_PIN ON -to Z1
set_instance_assignment -name VIRTUAL_PIN ON -to Z2
set_instance_assignment -name VIRTUAL_PIN ON -to Z3
set_instance_assignment -name VIRTUAL_PIN ON -to X1
set_global_assignment -name SYSTEMVERILOG_FILE HDL/primitives/arithmetic/add_4_parts.sv
set_global_assignment -name SYSTEMVERILOG_FILE HDL/primitives/arithmetic/add_8_parts.sv
set_global_assignment -name SYSTEMVERILOG_FILE HDL/primitives/arithmetic/sub.sv
set_global_assignment -name SYSTEMVERILOG_FILE HDL/parameters_pkg.sv
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top