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Implementation of a FPGA supported RISC-V CPU with 5-stage pipeline in SystemVerilog

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Computer Organization Lab @ Thinpad

Implemented a complete computer system on the ThinPAD-Cloud experimental platform. The ultimate goal is to support the operation of a 32-bit monitor program and run user-written assembly language programs. Specifically, the following were implemented:

  • A 32-bit RISC-V CPU with a clock speed of 40M.
  • Support for the basic version of the RV32I instruction set used by the monitor program.
  • Implementation of three additional instructions assigned to this group: PCNT, MINU, SBCLR.
  • Memory (SRAM) access capability to meet the storage needs of the monitor program’s data and code.
  • Utilized serial port to implement the computer’s input and output modules, supporting communication between the monitor program and the PC.
  • Implemented an interrupt handling mechanism to run an interrupt handling program to receive data in response to interrupt signals generated by the serial port.
  • Support for virtual memory management, separating the address spaces of the user program and the monitor program kernel.
  • Implemented dynamic branch prediction, cache, TLB to improve performance.
  • Support for Flash and VGA extensions, enabling the playback of videos stored in Flash.

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