[MBIST] Implement MBIST shared-bus in L2

src/main/scala/coupledL2/CoupledL2.scala

@@ -21,16 +21,19 @@ package coupledL2
 
 import chisel3._
 import chisel3.util._
-import utility.{FastArbiter, ParallelMax, ParallelPriorityMux, Pipeline, RegNextN, XSPerfAccumulate}
+import utility.{DFTResetSignals, FastArbiter, ParallelMax, ParallelPriorityMux, Pipeline, RegNextN, XSPerfAccumulate}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tile.MaxHartIdBits
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.tilelink.TLMessages._
 import freechips.rocketchip.util._
-import org.chipsalliance.cde.config.{Parameters, Field}
+import org.chipsalliance.cde.config.{Field, Parameters}
+
 import scala.math.max
 import coupledL2.prefetch._
-import huancun.{TPmetaReq, TPmetaResp, BankBitsKey}
+import huancun.{BankBitsKey, TPmetaReq, TPmetaResp}
+import utility.mbist.{MbistInterface, MbistPipeline}
+import utility.sram.SramHelper
 
 trait HasCoupledL2Parameters {
   val p: Parameters
@@ -533,5 +536,36 @@ abstract class CoupledL2Base(implicit p: Parameters) extends LazyModule with Has
 
     val okHint = grant_data_fire.orR && hintPipe1.io.out.valid && hintPipe1.io.out.bits === grant_data_source
     XSPerfAccumulate("ok2Hints", okHint)
+
+    private val mbistPl = MbistPipeline.PlaceMbistPipeline(Int.MaxValue, "L2Cache", cacheParams.hasMbist)
+
+    private val sigFromSrams = if (cacheParams.hasMbist) Some(SramHelper.genBroadCastBundleTop()) else None
+    val dft = if (cacheParams.hasMbist) Some(IO(sigFromSrams.get.cloneType)) else None
+    val dft_out = if (cacheParams.hasMbist) Some(IO(Output(sigFromSrams.get.cloneType))) else None
+    val dft_reset = IO(Input(new DFTResetSignals()))
+    val dft_reset_out = IO(Output(new DFTResetSignals()))
+    dft_reset_out := dft_reset
+    if (cacheParams.hasMbist) {
+      sigFromSrams.get := dft.get
+      dft_out.get := dft.get
+    }
+
+    private val l2MbistIntf = if (cacheParams.hasMbist) {
+      val params = mbistPl.get.nodeParams
+      val intf = Some(Module(new MbistInterface(
+        params = Seq(params),
+        ids = Seq(mbistPl.get.childrenIds),
+        name = s"MbistIntfL2",
+        pipelineNum = 1
+      )))
+      intf.get.toPipeline.head <> mbistPl.get.mbist
+      if (cacheParams.hartId == 0) mbistPl.get.registerCSV(intf.get.info, "MbistL2")
+      intf.get.mbist := DontCare
+      dontTouch(intf.get.mbist)
+      //TODO: add mbist controller connections here
+      intf
+    } else {
+      None
+    }
   }
 }

src/main/scala/coupledL2/DataStorage.scala

@@ -19,7 +19,10 @@ package coupledL2
 
 import chisel3._
 import chisel3.util._
-import coupledL2.utils.{HoldUnless, SRAMTemplate}
+import coupledL2.utils.HoldUnless
+import utility.SRAMTemplate
+import utility.mbist.MbistPipeline
+import utility.RegNextN
 import utility.ClockGate
 import org.chipsalliance.cde.config.Parameters
 
@@ -53,8 +56,10 @@ class DataStorage(implicit p: Parameters) extends L2Module {
     set = blocks,
     way = 1,
     singlePort = true,
-    readMCP2 = true
+    multicycle = 2,
+    hasMbist = p(L2ParamKey).hasMbist
   ))
+  private val mbistPl = MbistPipeline.PlaceMbistPipeline(1, "L2DataStorage", p(L2ParamKey).hasMbist)
 
   val masked_clock = ClockGate(false.B, io.req.valid, clock)
   array.clock := masked_clock

src/main/scala/coupledL2/Directory.scala

@@ -25,6 +25,8 @@ import utility.{ParallelPriorityMux, RegNextN, XSPerfAccumulate}
 import org.chipsalliance.cde.config.Parameters
 import coupledL2.prefetch.PfSource
 import freechips.rocketchip.tilelink.TLMessages._
+import utility.mbist.MbistPipeline
+import utility.{SRAMTemplate, HoldUnless}
 
 class MetaEntry(implicit p: Parameters) extends L2Bundle {
   val dirty = Bool()
@@ -129,8 +131,9 @@ class Directory(implicit p: Parameters) extends L2Module {
   val metaWen = io.metaWReq.valid
   val replacerWen = WireInit(false.B)
 
-  val tagArray  = Module(new SRAMTemplate(UInt(tagBits.W), sets, ways, singlePort = true))
-  val metaArray = Module(new SRAMTemplate(new MetaEntry, sets, ways, singlePort = true))
+  private val mbist = p(L2ParamKey).hasMbist
+  val tagArray  = Module(new SRAMTemplate(UInt(tagBits.W), sets, ways, singlePort = true, hasMbist = mbist))
+  val metaArray = Module(new SRAMTemplate(new MetaEntry, sets, ways, singlePort = true, hasMbist = mbist))
   val tagRead = Wire(Vec(ways, UInt(tagBits.W)))
   val metaRead = Wire(Vec(ways, new MetaEntry()))
 
@@ -141,7 +144,7 @@ class Directory(implicit p: Parameters) extends L2Module {
   val repl = ReplacementPolicy.fromString(cacheParams.replacement, ways)
   val random_repl = cacheParams.replacement == "random"
   val replacer_sram_opt = if(random_repl) None else
-    Some(Module(new SRAMTemplate(UInt(repl.nBits.W), sets, 1, singlePort = true, shouldReset = true)))
+    Some(Module(new SRAMTemplate(UInt(repl.nBits.W), sets, 1, singlePort = true, shouldReset = true, hasMbist = mbist)))
 
   /* ====== Generate response signals ====== */
   // hit/way calculation in stage 3, Cuz SRAM latency is high under high frequency
@@ -280,7 +283,7 @@ class Directory(implicit p: Parameters) extends L2Module {
   // hit-Promotion, miss-Insertion for RRIP
   // origin-bit marks whether the data_block is reused
   val origin_bit_opt = if(random_repl) None else
-    Some(Module(new SRAMTemplate(Bool(), sets, ways, singlePort = true, shouldReset = true)))
+    Some(Module(new SRAMTemplate(Bool(), sets, ways, singlePort = true, shouldReset = true, hasMbist = mbist)))
   val origin_bits_r = origin_bit_opt.get.io.r(io.read.fire, io.read.bits.set).resp.data
   val origin_bits_hold = Wire(Vec(ways, Bool()))
   origin_bits_hold := HoldUnless(origin_bits_r, RegNext(io.read.fire, false.B))
@@ -300,7 +303,7 @@ class Directory(implicit p: Parameters) extends L2Module {
     (!refillReqValid_s3 && req_s3.replacerInfo.channel(0) && req_s3.replacerInfo.opcode === Hint) || (req_s3.replacerInfo.channel(2) && metaAll_s3(way_s3).prefetch.getOrElse(false.B)) || (refillReqValid_s3 && req_s3.replacerInfo.refill_prefetch),
     req_s3.refill
   )
-
+  private val mbistPl = MbistPipeline.PlaceMbistPipeline(1, "L2Directory", mbist)
   if(cacheParams.replacement == "srrip"){
     val next_state_s3 = repl.get_next_state(repl_state_s3, way_s3, hit_s3, inv, rrip_req_type)
     val repl_init = Wire(Vec(ways, UInt(2.W)))

src/main/scala/coupledL2/L2Param.scala

@@ -106,7 +106,9 @@ case class L2Param(
   FPGAPlatform: Boolean = false,
 
   // Network layer SAM
-  sam: Seq[(AddressSet, Int)] = Seq(AddressSet.everything -> 0)
+  sam: Seq[(AddressSet, Int)] = Seq(AddressSet.everything -> 0),
+
+  hasMbist:Boolean = false
 ) {
   def toCacheParams: CacheParameters = CacheParameters(
     name = name,

src/main/scala/coupledL2/prefetch/BestOffsetPrefetch.scala

@@ -162,7 +162,7 @@ class RecentRequestTable(implicit p: Parameters) extends BOPModule {
   }
 
   val rrTable = Module(
-    new SRAMTemplate(rrTableEntry(), set = rrTableEntries, way = 1, shouldReset = true, singlePort = true)
+    new SRAMTemplate(rrTableEntry(), set = rrTableEntries, way = 1, shouldReset = true, singlePort = true, hasMbist = cacheParams.hasMbist)
   )
 
   val wAddr = io.w.bits

src/main/scala/coupledL2/prefetch/Prefetcher.scala

@@ -23,6 +23,7 @@ import utility._
 import org.chipsalliance.cde.config.Parameters
 import freechips.rocketchip.tilelink._
 import coupledL2._
+import utility.mbist.MbistPipeline
 
 /* virtual address */
 trait HasPrefetcherHelper extends HasCircularQueuePtrHelper with HasCoupledL2Parameters {
@@ -370,4 +371,5 @@ class Prefetcher(implicit p: Parameters) extends PrefetchModule {
   XSPerfAccumulate("prefetch_req_selectTP", hasTPReq && !hasReceiverReq && !hasVBOPReq && !hasPBOPReq)
   XSPerfAccumulate("prefetch_req_SMS_other_overlapped",
     hasReceiverReq && (hasVBOPReq || hasPBOPReq || hasTPReq))
+  private val mbistPl = MbistPipeline.PlaceMbistPipeline(2, "MbistPipeL2Prefetcher", cacheParams.hasMbist & hasBOP)
 }

src/main/scala/coupledL2/prefetch/TemporalPrefetch.scala

@@ -125,9 +125,9 @@ class TemporalPrefetch(implicit p: Parameters) extends TPModule {
     (x << 6.U).asUInt
   }
 
-  val tpMetaTable = Module(
-    new SRAMTemplate(new tpMetaEntry(), set = tpTableNrSet, way = tpTableAssoc, shouldReset = false, singlePort = true)
-  )
+  val tpMetaTable = Module(new SRAMTemplate(new tpMetaEntry(), set = tpTableNrSet, way = tpTableAssoc,
+    shouldReset = false, singlePort = true, hasMbist = cacheParams.hasMbist))
+
   val dataReadQueue = Module(new Queue(new TPmetaReq(), dataReadQueueDepth, pipe = false, flow = false))
   val dataWriteQueue = Module(new Queue(new TPmetaReq(), dataWriteQueueDepth, pipe = false, flow = false))
   val tpDataQueue = Module(new Queue(new tpDataEntry(), tpDataQueueDepth + 1, pipe = false, flow = false))

src/main/scala/coupledL2/tl2chi/Slice.scala

@@ -23,6 +23,7 @@ import freechips.rocketchip.tilelink._
 import org.chipsalliance.cde.config.Parameters
 import coupledL2._
 import coupledL2.prefetch.PrefetchIO
+import utility.mbist.MbistPipeline
 
 class OuterBundle(implicit p: Parameters) extends DecoupledPortIO with BaseOuterBundle
 
@@ -59,6 +60,7 @@ class Slice()(implicit p: Parameters) extends BaseSlice[OuterBundle]
   val mainPipe = Module(new MainPipe())
   val reqBuf = Module(new RequestBuffer())
   val mshrCtl = Module(new MSHRCtl())
+  private val mbistPl = MbistPipeline.PlaceMbistPipeline(2, "L2Slice", p(L2ParamKey).hasMbist)
 
   sinkC.io.msInfo := mshrCtl.io.msInfo
 

src/main/scala/coupledL2/utils/SRAMTemplate.scala

@@ -173,12 +173,6 @@ class SRAMTemplate[T <: Data]
       mem_rdata
     }).map(_.asTypeOf(gen))
 
-  if(clkDivBy2){
-    CustomAnnotations.annotateClkDivBy2(this)
-  }
-  if(!isPow2(set)){
-    CustomAnnotations.annotateSpecialDepth(this)
-  }
   if(readMCP2) {
     array.suggestName("array_mcp2")
   }