feat(CoupledL2): add flush L2 all operation #348

yulightenyu · 2025-01-23T03:57:53Z

  * Core initiate flush L2$ all operation by core and L2 interface <io.l2Flush>
  * The Barrier is added to wait all mshrs done before l2 flush begin
  * The FSM in SinkA is added to insert 'CBO_FLUSH' with set/way task to main pipe
  * The set/way are generated by the set loop（0~numSets） and way loop（0~numWays）
  * If cache-line is VALID, after CBO flush, main pipe sends back resp to SinkA
  * if cache-line is INVALID, main pipe drop it and send back resp to SinkA
  * During the process, SinkA/C is blocked by ready until l2 flush done
  * Snoop operations from SinkB is allowed to enter into main pipe
  * After all slices done, inform Core and exit coherency
  * fix tl2tl version with invalid <io.l2Flush>

… cacheline to release to memory * Core initiate flush L2$ all operation by core and L2 interface <io.l2Flush> * The Barrior is added to wait all mshrs done before l2 flush begin * The FSM in SinkA is added to insert 'CBO_FLUSH' with set/way task to main pipe * The set/way are generated by the set loop(0~numSets) and way loop(0~numWays) * If cacheline is VALID, after cbo flush, main pipe send back resp to sinkA * if cacheline is INVALID, main pipe drop it and send back resp to sinkA * During the process, sinkA/C is blocked by ready until l2 flush done * Snoop operations from sinkB is allowed to enter into mainpipe * After all slices done, inform Core and exit coherency

… cacheline to release to memory * Core initiate flush L2$ all operation by core and L2 interface <io.l2Flush> * The Barrior is added to wait all mshrs done before l2 flush begin * The FSM in SinkA is added to insert 'CBO_FLUSH' with set/way task to main pipe * The set/way are generated by the set loop(0~numSets) and way loop(0~numWays) * If cacheline is VALID, after cbo flush, main pipe send back resp to sinkA * if cacheline is INVALID, main pipe drop it and send back resp to sinkA * During the process, sinkA/C is blocked by ready until l2 flush done * Snoop operations from sinkB is allowed to enter into mainpipe * After all slices done, inform Core and exit coherency * fix tl2tl version with invalid io.l2Flush

… cacheline to release to memory * Core initiate flush L2$ all operation by core and L2 interface <io.l2Flush> * The Barrior is added to wait all mshrs done before l2 flush begin * The FSM in SinkA is added to insert 'CBO_FLUSH' with set/way task to main pipe * The set/way are generated by the set loop(0~numSets) and way loop(0~numWays) * If cacheline is VALID, after cbo flush, main pipe send back resp to sinkA * if cacheline is INVALID, main pipe drop it and send back resp to sinkA * During the process, sinkA/C is blocked by ready until l2 flush done * Snoop operations from sinkB is allowed to enter into mainpipe * After all slices done, inform Core and exit coherency

linjuanZ · 2025-02-08T07:29:03Z

src/main/scala/coupledL2/CoupledL2.scala

+//      val l2Flush = Option.when(cacheParams.enableL2Flush) (Input(Bool()))
+//      val l2FlushDone = Option.when(cacheParams.enableL2Flush) (Output(Bool()))


Stale comments should be removed.

linjuanZ · 2025-02-08T07:29:15Z

src/main/scala/coupledL2/CoupledL2.scala

@@ -435,6 +438,9 @@ abstract class CoupledL2Base(implicit p: Parameters) extends LazyModule with Has

        slice.io.error.ready := enableECC.asBool // TODO: fix the datapath as optional

+//      slice.io.l2Flush.foreach(_ := io.l2Flush.getOrElse(false.B))


Stale comments should be removed.

linjuanZ · 2025-02-08T07:29:24Z

src/main/scala/coupledL2/CoupledL2.scala

+    //L2 Flush Done
+    //io.l2FlushDone.foreach(_ :=  VecInit(slices.zipWithIndex.map { case (s, i) => s.io.l2FlushDone.getOrElse(false.B)}).reduce(_&_) )
+


Stale comments should be removed.

linjuanZ · 2025-02-08T07:33:39Z

src/main/scala/coupledL2/Common.scala

@@ -108,6 +108,7 @@ class TaskBundle(implicit p: Parameters) extends L2Bundle

  // for CMO
  val cmoTask = Bool()
+  val cmoAll = Bool()


Comment needed here.

linjuanZ · 2025-02-08T07:33:44Z

src/main/scala/coupledL2/Common.scala

+class IOCMOAll(implicit p: Parameters) extends Bundle {
+  val l2Flush = Input(Bool())
+  val l2FlushDone = Output(Bool())
+
+  val cmoLineDone = Input(Bool())
+  val mshrValid = Input(Bool())
+  val cmoAllBlock = Output(Bool())
+}


Comment needed here.

linjuanZ · 2025-02-08T07:44:18Z

src/main/scala/coupledL2/SinkA.scala

+  val cmoAllValid = (state === sCMOREQ)
+  val cmoAllBlock = (state === sCMOREQ) || (state === sWAITLINE)
+  io.cmoAll.foreach {cmoAll => cmoAll.l2FlushDone :=(state ===sDONE)}


Remove redundant brackets.

linjuanZ · 2025-02-08T07:44:54Z

src/main/scala/coupledL2/SinkA.scala

    task.off := parseAddress(a.address)._3
    task.alias.foreach(_ := a.user.lift(AliasKey).getOrElse(0.U))
-    task.opcode := a.opcode
+    task.opcode := Mux(cmoAllValid, 13.U, a.opcode)


What is 13?

linjuanZ · 2025-02-08T07:51:26Z

src/main/scala/coupledL2/SinkA.scala

+  when (state === sIDLE && l2Flush && !mshrValid) {
+    state := sCMOREQ
+  }
+  when ((state === sCMOREQ) && io.task.fire) {
+    state := sWAITLINE
+  }
+  when (state === sWAITLINE && cmoLineDone) {
+    when (set===(numSets-1).U && way===(numWays-1).U) { 
+      state := sDONE
+    }.otherwise {
+      when(way ===(numWays -1).U) {
+        way:=0.U
+        set:=set+1.U
+      }.otherwise {
+        way:=way+1.U
+      }
+      when (mshrValid) {
+        state := sCMOREQ
+      }.otherwise {
+        state := sWAITMSHR
+      }
+    }
+  }
+  when ((state === sWAITMSHR) && !mshrValid) {
+    state := sCMOREQ


Please read the coding standards carefully.

linjuanZ · 2025-02-08T07:52:37Z

src/main/scala/coupledL2/tl2chi/MainPipe.scala


  val mshr_req_s3     = req_s3.mshrTask
  val sink_req_s3     = !mshr_req_s3
  val sinkA_req_s3    = !mshr_req_s3 && req_s3.fromA
  val sinkB_req_s3    = !mshr_req_s3 && req_s3.fromB
  val sinkC_req_s3    = !mshr_req_s3 && req_s3.fromC
-
+  


Blank lines should not contain spaces.

linjuanZ · 2025-02-08T07:59:07Z

src/main/scala/coupledL2/tl2chi/MainPipe.scala

+  val cmoLineDrop = io.cmoAllBlock.getOrElse(false.B) && task_s3.valid && sinkA_req_s3 && (req_s3.opcode === CBOFlush) && (meta_s3.state === INVALID)
+  val cmoLineDone = io.cmoAllBlock.getOrElse(false.B) && task_s3.valid && mshr_cmoresp_s3
+  io.cmoLineDone.foreach{_ := RegNextN( ( cmoLineDone || cmoLineDrop) , 2, Some(false.B))}


Please read the coding standards carefully.

yulightenyu added 3 commits January 22, 2025 16:37

yulightenyu requested review from Ivyfeather, Kumonda221-CrO3 and linjuanZ as code owners January 23, 2025 03:57

yulightenyu added 2 commits January 23, 2025 14:06

linjuanZ requested changes Feb 8, 2025

View reviewed changes

linjuanZ changed the title ~~feat(TL2CIHCoupledL2): add flush L2 all operation to search all VALID cache-line to release to memory~~ feat(CoupledL2): add flush L2 all operation Feb 8, 2025

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feat(CoupledL2): add flush L2 all operation #348

feat(CoupledL2): add flush L2 all operation #348

yulightenyu commented Jan 23, 2025

linjuanZ Feb 8, 2025

linjuanZ Feb 8, 2025

linjuanZ Feb 8, 2025

linjuanZ Feb 8, 2025

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linjuanZ Feb 8, 2025

linjuanZ Feb 8, 2025

linjuanZ Feb 8, 2025

		// val l2Flush = Option.when(cacheParams.enableL2Flush) (Input(Bool()))
		// val l2FlushDone = Option.when(cacheParams.enableL2Flush) (Output(Bool()))

		@@ -435,6 +438,9 @@ abstract class CoupledL2Base(implicit p: Parameters) extends LazyModule with Has

		slice.io.error.ready := enableECC.asBool // TODO: fix the datapath as optional

		// slice.io.l2Flush.foreach(_ := io.l2Flush.getOrElse(false.B))

		//L2 Flush Done
		//io.l2FlushDone.foreach(_ := VecInit(slices.zipWithIndex.map { case (s, i) => s.io.l2FlushDone.getOrElse(false.B)}).reduce(_&_) )

feat(CoupledL2): add flush L2 all operation #348

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feat(CoupledL2): add flush L2 all operation #348

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yulightenyu commented Jan 23, 2025

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