cpu-o3: update UFTB ctr when UFTB hit but condTaken diff from s1 pred

src/cpu/pred/ftb/decoupled_bpred.cc

@@ -851,7 +851,7 @@ DecoupledBPUWithFTB::generateFinalPredAndCreateBubbles()
             if (first_hit_stage == 1) {
                 assert(predsOfEachStage[1].valid);
 
-                for (int b = 0; b < numBr; ++b){
+                for (int b = 0; b < numBr; ++b) {
                     if (b < predsOfEachStage[1].ftbEntry.slots.size()){
                         Addr slot_pc = predsOfEachStage[1].ftbEntry.slots[b].pc;
                         auto it = s1PrevPredTakens.find(slot_pc);
@@ -890,6 +890,7 @@ DecoupledBPUWithFTB::generateFinalPredAndCreateBubbles()
                         if (s0_entry_slot.condValid() && s1_entry_slot.condValid()) {
                             if (s0_entry_slot.pc == s1_entry_slot.pc && s0_condTakens[b] != s1_condTakens[b]) {
                                 dbpFtbStats.overrideByL1WhenL0HitButTakenDiff++;
+                                uftb->updateUftbWhenOverrideByL1(predsOfEachStage[0].bbStart, b, s1_condTakens[b]);
                                 break;
                             } else if (s0_entry_slot.pc == s1_entry_slot.pc && s0_condTakens[b] == 1 && s1_condTakens[b] == 1) {
                                 assert(0); // if taken, then predsOfEachStage0 should equal to predsOfEachStage1

src/cpu/pred/ftb/ftb.cc

@@ -32,6 +32,7 @@
 #include "cpu/o3/dyn_inst.hh"
 #include "cpu/pred/ftb/ftb.hh"
 #include "debug/Fetch.hh"
+#include "debug/Override.hh"
 
 namespace gem5
 {
@@ -501,6 +502,32 @@ DefaultFTB::update(const FetchStream &stream)
     // ftb[ftb_idx].tag = getTag(inst_pc);
 }
 
+void
+DefaultFTB::updateUftbWhenOverrideByL1(Addr bbStart, int brIdx, bool condTaken){
+    assert(getDelay() == 0);
+
+    Addr ftb_idx = getIndex(bbStart);
+    Addr ftb_tag = getTag(bbStart);
+
+    auto it = ftb[ftb_idx].find(ftb_tag);
+    bool not_found = it == ftb[ftb_idx].end();
+    assert(!not_found);
+
+    auto entry_to_update = ftb[ftb_idx][ftb_tag];
+    DPRINTF(OverrideByL1, "=============================\n");
+    DPRINTF(OverrideByL1, "s1 Taken: %d, brIdx: %d\n", condTaken, brIdx);
+    printFTBEntryWhenOverrideByL1(entry_to_update);
+
+    updateCtr(entry_to_update.slots[brIdx].ctr, condTaken); // only update the ctr
+    ftb[ftb_idx][ftb_tag] = entry_to_update;
+
+    DPRINTF(OverrideByL1, "-----------------------------\n");
+
+    printFTBEntryWhenOverrideByL1(entry_to_update);
+
+    DPRINTF(OverrideByL1, "=============================\n");
+}
+
 void
 DefaultFTB::commitBranch(const FetchStream &stream, const DynInstPtr &inst)
 {

src/cpu/pred/ftb/ftb.hh

@@ -37,6 +37,7 @@
 #include "cpu/pred/ftb/timed_base_pred.hh"
 #include "debug/FTB.hh"
 #include "debug/FTBStats.hh"
+#include "debug/OverrideByL1.hh"
 #include "params/DefaultFTB.hh"
 
 
@@ -118,6 +119,8 @@ class DefaultFTB : public TimedBaseFTBPredictor
      */
     void update(const FetchStream &stream) override;
 
+    void updateUftbWhenOverrideByL1(Addr bbStart, int brIdx, bool condTaken);
+
     void commitBranch(const FetchStream &stream, const DynInstPtr &inst) override;
 
     /**
@@ -185,6 +188,15 @@ class DefaultFTB : public TimedBaseFTBPredictor
         }
     }
 
+    void printFTBEntryWhenOverrideByL1(const FTBEntry &entry) {
+        DPRINTF(OverrideByL1, "FTB entry: valid %d, tag %#lx, fallThruAddr:%#lx, slots:\n",
+            entry.valid, entry.tag, entry.fallThruAddr);
+        for (auto &slot : entry.slots) {
+            DPRINTF(OverrideByL1, "    valid %d, pc:%#lx, size:%d, target:%#lx, ctr:%d, cond:%d, indirect:%d, call:%d, return:%d\n",
+                slot.valid, slot.pc, slot.size, slot.target, slot.ctr, slot.isCond, slot.isIndirect, slot.isCall, slot.isReturn);
+        }
+    }
+
     void printTickedFTBEntry(TickedFTBEntry &e) {
         printFTBEntry(e, e.tick);
     }