Merge remote-tracking branch 'upstream/master' into master #26
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Support RocketChip build Chisel from source
Bump to Chisel 5.1
Support vector-units w/o L1D$ access
(cherry picked from commit df66c19)
(cherry picked from commit 74dd9b1)
(cherry picked from commit 5bef59a) # Conflicts: # src/main/scala/tile/Core.scala
(cherry picked from commit 218ae0a)
…/master/pr-3532 Remove Scalar Crypto and BitManip (copy chipsalliance#3532)
…d by the manuals. * Fix the mapping when we access scontext or hcontext to ensure we don't switch targets. * Add comment to indicate why we are mapping the S to VS and VS to S.
SContext is remaps to HContext when in VSMode
Fix support for vector units with Zvfh
Support vector extensions
Prevent bypasses from vector instructions | fix vsets
Sync dev to master
There is a naming conflict of the ALU module which prevents a successful synthesis with Yosys. This patch fixes this conflict. In addition, this patch introduces the configurations expected by Litex when generating an SoC This patch also adds a generator for System Verilog which works with Yosys
Add approved RocketChip technical charter to the project repository.
…-patch-1 Add RocketChip Technical Charter
…g_rocc_bug_fix_issue3695 Rocket Core Clock Gate Bug Fix
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