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Openpiton Support for NetFPGA-SUME board #76

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Openpiton Support for NetFPGA-SUME board #76

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fbeb417
added the SUME ip cores
MinaAbbasi May 27, 2020
724179f
changed tcl files to add sume specific ip cores to project
MinaAbbasi May 27, 2020
7c87922
added sume properties to board.tcl
MinaAbbasi May 27, 2020
4c643fa
added SUME characteristics to fpga_lib
MinaAbbasi May 27, 2020
6e33778
added changes for SUME board
MinaAbbasi May 27, 2020
e1ab9e8
added changes for SUME board
MinaAbbasi May 27, 2020
00a17df
added changes for SUME board
MinaAbbasi May 27, 2020
ad9957b
added changes for SUME board
MinaAbbasi May 27, 2020
0f7f751
added sume to the boards list
MinaAbbasi May 27, 2020
df10868
change protosyn to comply with sume
MinaAbbasi May 27, 2020
faf1ac6
added the sume directory in tools
MinaAbbasi May 27, 2020
86b2a46
removed absolute paths from fpga_lib.by
MinaAbbasi Jun 8, 2020
48f5a51
removed extra print in fpga_lib.py
MinaAbbasi Jun 8, 2020
ace7609
change the gen_project.tcl to original
MinaAbbasi Jun 9, 2020
627dffe
removing switch part for sume board in system.v
MinaAbbasi Jun 9, 2020
151a1f1
now we have just one constraint file
MinaAbbasi Jun 9, 2020
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18 changes: 18 additions & 0 deletions piton/design/chipset/include/mc_define.h
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Expand Up @@ -159,6 +159,24 @@
`define DDR3_CKE_WIDTH 1
`define DDR3_CS_WIDTH 1
`define DDR3_ODT_WIDTH 1
`elsif SUME_BOARD
`define BOARD_MEM_SIZE_MB 4096
`define WORDS_PER_BURST 8
`define WORD_SIZE 8 // in bytes
`define MIG_APP_ADDR_WIDTH 30
`define MIG_APP_CMD_WIDTH 3
`define MIG_APP_DATA_WIDTH 512
`define MIG_APP_MASK_WIDTH 64

`define DDR3_DQ_WIDTH 64
`define DDR3_DQS_WIDTH 8
`define DDR3_ADDR_WIDTH 16
`define DDR3_BA_WIDTH 3
`define DDR3_DM_WIDTH 8
`define DDR3_CK_WIDTH 1
`define DDR3_CKE_WIDTH 1
`define DDR3_CS_WIDTH 1
`define DDR3_ODT_WIDTH 1
`else
`define BOARD_MEM_SIZE_MB 1024
`define MIG_APP_ADDR_WIDTH 29
Expand Down
634 changes: 634 additions & 0 deletions piton/design/chipset/io_ctrl/xilinx/sume/ip_cores/atg_uart_init/atg_uart_init.xci
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Empty file added piton/design/chipset/io_ctrl/xilinx/sume/ip_cores/atg_uart_init/dummy.coe
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2 changes: 2 additions & 0 deletions piton/design/chipset/io_ctrl/xilinx/sume/ip_cores/atg_uart_init/uart_addr.coe
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@@ -0,0 +1,2 @@
memory_initialization_radix=16;
memory_initialization_vector=0000100C 00001000 00001004 0000100C 00001004 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000;
2 changes: 2 additions & 0 deletions piton/design/chipset/io_ctrl/xilinx/sume/ip_cores/atg_uart_init/uart_data.coe
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@@ -0,0 +1,2 @@
memory_initialization_radix=16;
memory_initialization_vector=00000080 00000024 00000000 00000003 00000003 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000;
320 changes: 320 additions & 0 deletions piton/design/chipset/io_ctrl/xilinx/sume/ip_cores/bram_16384x512/bram_16384x512.xci
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16,386 changes: 16,386 additions & 0 deletions piton/design/chipset/io_ctrl/xilinx/sume/ip_cores/bram_16384x512/obp.coe
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320 changes: 320 additions & 0 deletions piton/design/chipset/io_ctrl/xilinx/sume/ip_cores/bram_256x512/bram_256x512.xci
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119 changes: 119 additions & 0 deletions piton/design/chipset/io_ctrl/xilinx/sume/ip_cores/uart_16550/uart_16550.xci
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@@ -0,0 +1,119 @@
<?xml version="1.0" encoding="UTF-8"?>
<spirit:design xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
<spirit:vendor>xilinx.com</spirit:vendor>
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<spirit:name>unknown</spirit:name>
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<spirit:instanceName>uart_16550</spirit:instanceName>
<spirit:componentRef spirit:vendor="xilinx.com" spirit:library="ip" spirit:name="axi_uart16550" spirit:version="2.0"/>
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<spirit:configurableElementValue spirit:referenceId="PARAM_VALUE.C_HAS_EXTERNAL_RCLK">0</spirit:configurableElementValue>
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<spirit:configurableElementValue spirit:referenceId="PROJECT_PARAM.SILICON_REVISION"/>
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<xilinx:componentInstanceExtensions>
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</spirit:design>
37 changes: 34 additions & 3 deletions piton/design/chipset/mc/rtl/mc_top.v
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Original file line number Diff line number Diff line change
Expand Up @@ -51,8 +51,15 @@ module mc_top (
output ddr_act_n,
output [`DDR3_BG_WIDTH-1:0] ddr_bg,
`else // PITONSYS_DDR4
`ifndef SUME_BOARD
input sys_clk,

`else
input sys_clk_n,
input sys_clk_p,
input clk_ref_n,
input clk_ref_p,
output ui_clk,
`endif
output ddr_cas_n,
output ddr_ras_n,
output ddr_we_n,
Expand Down Expand Up @@ -82,7 +89,8 @@ module mc_top (
output [`DDR3_ODT_WIDTH-1:0] ddr_odt,

output init_calib_complete_out,
input sys_rst_n
input sys_rst_n,
output mmcm_locked
);
reg [31:0] delay_cnt;
reg ui_clk_syn_rst_delayed;
Expand Down Expand Up @@ -626,13 +634,25 @@ mig_7series_0 mig_7series_0 (
.app_rd_data_valid (app_rd_data_valid),
.app_rdy (app_rdy),
.app_wdf_rdy (app_wdf_rdy),
.app_wdf_mask (app_wdf_mask),
// System Clock Ports
`ifndef SUME_BOARD
.sys_clk_i (sys_clk),
`else
.sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
`endif
.app_sr_req (app_sr_req),
.app_ref_req (app_ref_req),
.app_zq_req (app_zq_req),
.app_sr_active (app_sr_active),
.app_ref_ack (app_ref_ack),
.app_zq_ack (app_zq_ack),
.ui_clk (ui_clk),
`ifdef SUME_BOARD
.clk_ref_p (clk_ref_p), // input clk_ref_p
.clk_ref_n (clk_ref_n), // input clk_ref_n
`endif
.ui_clk_sync_rst (ui_clk_sync_rst),
.app_wdf_mask (app_wdf_mask),

Expand Down Expand Up @@ -1049,7 +1069,7 @@ mig_7series_axi4 u_mig_7series_axi4 (
// Application interface ports
.ui_clk (ui_clk), // output ui_clk
.ui_clk_sync_rst (ui_clk_sync_rst), // output ui_clk_sync_rst
.mmcm_locked (), // output mmcm_locked
.mmcm_locked (mmcm_locked), // output mmcm_locked
.aresetn (sys_rst_n), // input aresetn
.app_sr_req (app_sr_req), // input app_sr_req
.app_ref_req (app_ref_req), // input app_ref_req
Expand Down Expand Up @@ -1102,7 +1122,18 @@ mig_7series_axi4 u_mig_7series_axi4 (
.s_axi_rready (m_axi_rready), // input s_axi_rready

// System Clock Ports
// .sys_clk_i (sys_clk),
`ifndef SUME_BOARD
.sys_clk_i (sys_clk),
`else
.sys_clk_p (sys_clk_p),
.sys_clk_n (sys_clk_n),
`endif

`ifdef SUME_BOARD
.clk_ref_p (clk_ref_p), // input clk_ref_p
.clk_ref_n (clk_ref_n), // input clk_ref_n
`endif
.sys_rst (sys_rst_n) // input sys_rst
);

Expand Down
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