Skip to content

Commit 2864ced

Browse files
committed
openflow: properly re-added VHDL support
Closes #51
1 parent 01991d7 commit 2864ced

File tree

3 files changed

+6
-8
lines changed

3 files changed

+6
-8
lines changed

examples/projects/regress.sh

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -25,9 +25,6 @@ for TOOL in "${!TOOLS[@]}"; do
2525
if [[ "$TOOL" == "ise" && "$SOURCE" == "slog" ]]; then
2626
continue
2727
fi
28-
if [[ "$TOOL" == "openflow" && "$SOURCE" == "vhdl" ]]; then
29-
continue
30-
fi
3128
echo "> $TOOL - $BOARD - $SOURCE"
3229
python3 $TOOL.py --board $BOARD --source $SOURCE
3330
done

pyfpga/project.py

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -83,13 +83,15 @@ def _add_file(self, pathname, hdl=None, lib=None):
8383
if len(files) == 0:
8484
raise FileNotFoundError(pathname)
8585
for file in files:
86-
path = Path(file).resolve()
86+
path = Path(file).resolve().as_posix()
8787
attr = {}
8888
if hdl:
8989
attr['hdl'] = hdl
9090
if lib:
9191
attr['lib'] = lib
92-
self.data.setdefault('files', {})[path.as_posix()] = attr
92+
if path in self.data.get('files', {}):
93+
del self.data['files'][path]
94+
self.data.setdefault('files', {})[path] = attr
9395

9496
def add_slog(self, pathname):
9597
"""Add System Verilog file/s.

pyfpga/templates/openflow.jinja

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -15,14 +15,13 @@ $DOCKER hdlc/ghdl:yosys /bin/bash -c "
1515
{% if hooks %}{{ hooks.presyn | join('\n') }}{% endif %}
1616

1717
{% set gflags = '--std=08 -fsynopsys -fexplicit -frelaxed' %}
18-
{% if files %}# Files inclusion
18+
{% if files %}# VHDL Files inclusion
1919
{% for name, attr in files.items() %}
2020
{% if attr.hdl == "vhdl" %}
2121
ghdl -a {{ gflags }}{% if 'lib' in attr %} --work={{ attr.lib }}{% endif %} {{ name }}
2222
{% endif %}
2323
{% endfor %}
2424
{% endif %}
25-
ghdl -a --std=08 -fsynopsys -fexplicit -frelaxed /home/rodrigo/repos-ram/PyFPGA/pyfpga/examples/sources/vhdl/top.vhdl
2625

2726
yosys -Q -m ghdl -p '
2827

@@ -34,7 +33,7 @@ verilog_defaults -add{% for path in includes %} -I{{ path }}{% endfor %}
3433
verilog_defines{% for key, value in defines.items() %} -D{{ key }}={{ value }}{% endfor %}
3534
{% endif %}
3635

37-
{% if files %}# Files inclusion
36+
{% if files %}# VLOG Files inclusion
3837
{% for name, attr in files.items() %}
3938
{% if attr.hdl == "vlog" %}
4039
read_verilog -defer {{ name }}

0 commit comments

Comments
 (0)