This repo contains Verilog code and testbenches from the Computer Architecture lab. The highlight is a simple RISC-V single-cycle processor that supports 7 instructions:
- add – Performs addition of two registers and stores the result in the destination register.
- sub – Subtracts the value of one register from another and stores the result.
- and – Executes a bitwise AND operation between two registers.
- or – Executes a bitwise OR operation between two registers.
- lw – Loads a word from memory into a register.
- sw – Stores the contents of a register into memory.
- beq – Compares two registers and branches to a specified address if they are equal.
These instructions form the core of basic computational and control operations, providing the foundational framework for more complex architectures.