Merge branch 'master' into develop-documentation

.github/workflows/ci.yml

@@ -106,7 +106,7 @@ jobs:
           make tests -s > /dev/null
 
       - name: Upload Build Artifact
-        uses: actions/upload-artifact@v3
+        uses: actions/upload-artifact@v4
         with:
           name: build-${{ matrix.xlen }}
           path: build${{ matrix.xlen }}
@@ -147,7 +147,7 @@ jobs:
             ${{ runner.os }}-thirdparty-
 
       - name: Download Build Artifact
-        uses: actions/download-artifact@v3
+        uses: actions/download-artifact@v4
         with:
           name: build-${{ matrix.xlen }}
           path: build${{ matrix.xlen }}

ci/regression.sh.in

@@ -301,11 +301,11 @@ config2()
 
     # test single-bank memory
     if [ "$XLEN" == "64" ]; then
-        CONFIGS="-DPLATFORM_MEMORY_BANKS=1 -DPLATFORM_MEMORY_ADDR_WIDTH=48" ./ci/blackbox.sh --driver=opae --app=mstress
-        CONFIGS="-DPLATFORM_MEMORY_BANKS=1 -DPLATFORM_MEMORY_ADDR_WIDTH=48" ./ci/blackbox.sh --driver=xrt --app=mstress
+        CONFIGS="-DPLATFORM_MEMORY_NUM_BANKS=1" ./ci/blackbox.sh --driver=opae --app=mstress
+        CONFIGS="-DPLATFORM_MEMORY_NUM_BANKS=1" ./ci/blackbox.sh --driver=xrt --app=mstress
     else
-        CONFIGS="-DPLATFORM_MEMORY_BANKS=1 -DPLATFORM_MEMORY_ADDR_WIDTH=32" ./ci/blackbox.sh --driver=opae --app=mstress
-        CONFIGS="-DPLATFORM_MEMORY_BANKS=1 -DPLATFORM_MEMORY_ADDR_WIDTH=32" ./ci/blackbox.sh --driver=xrt --app=mstress
+        CONFIGS="-DPLATFORM_MEMORY_NUM_BANKS=1" ./ci/blackbox.sh --driver=opae --app=mstress
+        CONFIGS="-DPLATFORM_MEMORY_NUM_BANKS=1" ./ci/blackbox.sh --driver=xrt --app=mstress
     fi
 
     # test larger memory address
@@ -322,10 +322,10 @@ config2()
     CONFIGS="-DPLATFORM_MEMORY_INTERLEAVE=0" ./ci/blackbox.sh --driver=opae --app=mstress
 
     # test memory ports
-    CONFIGS="-DMEM_BLOCK_SIZE=8 -DPLATFORM_MEMORY_BANKS=2" ./ci/blackbox.sh --driver=simx --app=mstress
-    CONFIGS="-DMEM_BLOCK_SIZE=8 -DPLATFORM_MEMORY_BANKS=2" ./ci/blackbox.sh --driver=simx --app=mstress --threads=8
-    CONFIGS="-DMEM_BLOCK_SIZE=8 -DPLATFORM_MEMORY_BANKS=2" ./ci/blackbox.sh --driver=rtlsim --app=mstress
-    CONFIGS="-DMEM_BLOCK_SIZE=8 -DPLATFORM_MEMORY_BANKS=2" ./ci/blackbox.sh --driver=rtlsim --app=mstress --threads=8
+    CONFIGS="-DMEM_BLOCK_SIZE=8 -DPLATFORM_MEMORY_NUM_BANKS=2" ./ci/blackbox.sh --driver=simx --app=mstress
+    CONFIGS="-DMEM_BLOCK_SIZE=8 -DPLATFORM_MEMORY_NUM_BANKS=2" ./ci/blackbox.sh --driver=simx --app=mstress --threads=8
+    CONFIGS="-DMEM_BLOCK_SIZE=8 -DPLATFORM_MEMORY_NUM_BANKS=2" ./ci/blackbox.sh --driver=rtlsim --app=mstress
+    CONFIGS="-DMEM_BLOCK_SIZE=8 -DPLATFORM_MEMORY_NUM_BANKS=2" ./ci/blackbox.sh --driver=rtlsim --app=mstress --threads=8
     CONFIGS="-DMEM_BLOCK_SIZE=8" ./ci/blackbox.sh --driver=opae --app=mstress --threads=8
     CONFIGS="-DMEM_BLOCK_SIZE=8" ./ci/blackbox.sh --driver=xrt --app=mstress --threads=8
 

hw/rtl/VX_config.vh

@@ -172,8 +172,26 @@
 `define L3_LINE_SIZE `MEM_BLOCK_SIZE
 `endif
 
-`ifndef PLATFORM_MEMORY_BANKS
-`define PLATFORM_MEMORY_BANKS 2
+// Platform memory parameters
+
+`ifndef PLATFORM_MEMORY_NUM_BANKS
+`define PLATFORM_MEMORY_NUM_BANKS 2
+`endif
+
+`ifndef PLATFORM_MEMORY_ADDR_WIDTH
+`ifdef XLEN_64
+    `define PLATFORM_MEMORY_ADDR_WIDTH 48
+`else
+    `define PLATFORM_MEMORY_ADDR_WIDTH 32
+`endif
+`endif
+
+`ifndef PLATFORM_MEMORY_DATA_SIZE
+`define PLATFORM_MEMORY_DATA_SIZE 64
+`endif
+
+`ifndef PLATFORM_MEMORY_INTERLEAVE
+`define PLATFORM_MEMORY_INTERLEAVE 1
 `endif
 
 `ifdef XLEN_64
@@ -656,9 +674,9 @@
 // Number of Memory Ports
 `ifndef L1_MEM_PORTS
 `ifdef L1_DISABLE
-`define L1_MEM_PORTS `MIN(DCACHE_NUM_REQS, `PLATFORM_MEMORY_BANKS)
+`define L1_MEM_PORTS `MIN(DCACHE_NUM_REQS, `PLATFORM_MEMORY_NUM_BANKS)
 `else
-`define L1_MEM_PORTS `MIN(`DCACHE_NUM_BANKS, `PLATFORM_MEMORY_BANKS)
+`define L1_MEM_PORTS `MIN(`DCACHE_NUM_BANKS, `PLATFORM_MEMORY_NUM_BANKS)
 `endif
 `endif
 
@@ -735,9 +753,9 @@
 // Number of Memory Ports
 `ifndef L2_MEM_PORTS
 `ifdef L2_ENABLE
-`define L2_MEM_PORTS `MIN(`L2_NUM_BANKS, `PLATFORM_MEMORY_BANKS)
+`define L2_MEM_PORTS `MIN(`L2_NUM_BANKS, `PLATFORM_MEMORY_NUM_BANKS)
 `else
-`define L2_MEM_PORTS `MIN(L2_NUM_REQS, `PLATFORM_MEMORY_BANKS)
+`define L2_MEM_PORTS `MIN(L2_NUM_REQS, `PLATFORM_MEMORY_NUM_BANKS)
 `endif
 `endif
 
@@ -796,9 +814,9 @@
 // Number of Memory Ports
 `ifndef L3_MEM_PORTS
 `ifdef L3_ENABLE
-`define L3_MEM_PORTS `MIN(`L3_NUM_BANKS, `PLATFORM_MEMORY_BANKS)
+`define L3_MEM_PORTS `MIN(`L3_NUM_BANKS, `PLATFORM_MEMORY_NUM_BANKS)
 `else
-`define L3_MEM_PORTS `MIN(L3_NUM_REQS, `PLATFORM_MEMORY_BANKS)
+`define L3_MEM_PORTS `MIN(L3_NUM_REQS, `PLATFORM_MEMORY_NUM_BANKS)
 `endif
 `endif
 

hw/rtl/Vortex_axi.sv

@@ -193,7 +193,7 @@ module Vortex_axi import VX_gpu_pkg::*; #(
         .TAG_WIDTH_OUT  (AXI_TID_WIDTH),
         .NUM_PORTS_IN   (`VX_MEM_PORTS),
         .NUM_BANKS_OUT  (AXI_NUM_BANKS),
-        .INTERLEAVE     (0),
+        .INTERLEAVE     (`PLATFORM_MEMORY_INTERLEAVE),
         .REQ_OUT_BUF    ((`VX_MEM_PORTS > 1) ? 2 : 0),
         .RSP_OUT_BUF    ((`VX_MEM_PORTS > 1 || AXI_NUM_BANKS > 1) ? 2 : 0)
     ) axi_adapter (

hw/rtl/afu/opae/local_mem_cfg_pkg.sv

@@ -28,18 +28,18 @@
 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 // POSSIBILITY OF SUCH DAMAGE.
 
-//`include "platform_afu_top_config.vh"
+`include "VX_define.vh"
 
 `ifndef PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH
-`define PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH (`PLATFORM_MEMORY_ADDR_WIDTH - $clog2(`PLATFORM_MEMORY_DATA_WIDTH/8))
+`define PLATFORM_PARAM_LOCAL_MEMORY_ADDR_WIDTH ((`PLATFORM_MEMORY_ADDR_WIDTH - $clog2(`PLATFORM_MEMORY_NUM_BANKS)) - $clog2(`PLATFORM_MEMORY_DATA_SIZE))
 `endif
 
 `ifndef PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH
-`define PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH `PLATFORM_MEMORY_DATA_WIDTH
+`define PLATFORM_PARAM_LOCAL_MEMORY_DATA_WIDTH (`PLATFORM_MEMORY_DATA_SIZE * 8)
 `endif
 
 `ifndef PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH
-`define PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH `PLATFORM_MEMORY_BURST_CNT_WIDTH
+`define PLATFORM_PARAM_LOCAL_MEMORY_BURST_CNT_WIDTH 4
 `endif
 
 package local_mem_cfg_pkg;

hw/rtl/afu/opae/vortex_afu.sv

@@ -11,18 +11,14 @@
 // See the License for the specific language governing permissions and
 // limitations under the License.
 
+`include "VX_define.vh"
+
 `ifndef NOPAE
 `include "afu_json_info.vh"
 `else
 `include "vortex_afu.vh"
 `endif
 
-`include "VX_define.vh"
-
-`ifndef PLATFORM_MEMORY_INTERLEAVE
-`define PLATFORM_MEMORY_INTERLEAVE 1
-`endif
-
 module vortex_afu import ccip_if_pkg::*; import local_mem_cfg_pkg::*; import VX_gpu_pkg::*; #(
     parameter NUM_LOCAL_MEM_BANKS = 2
 ) (

hw/rtl/afu/xrt/VX_afu_ctrl.sv

@@ -134,10 +134,12 @@ module VX_afu_ctrl #(
         RSTATE_RESP     = 2'd2,
         RSTATE_WIDTH    = 2;
 
+    localparam MEMORY_BANK_ADDR_WIDTH = `PLATFORM_MEMORY_ADDR_WIDTH - `CLOG2(`PLATFORM_MEMORY_NUM_BANKS);
+
     // device caps
     wire [63:0] dev_caps = {8'b0,
-                            5'(`PLATFORM_MEMORY_ADDR_WIDTH-20),
-                            3'(`CLOG2(`PLATFORM_MEMORY_BANKS)),
+                            5'(MEMORY_BANK_ADDR_WIDTH-20),
+                            3'(`CLOG2(`PLATFORM_MEMORY_NUM_BANKS)),
                             8'(`LMEM_ENABLED ? `LMEM_LOG_SIZE : 0),
                             16'(`NUM_CORES * `NUM_CLUSTERS),
                             8'(`NUM_WARPS),

hw/rtl/afu/xrt/VX_afu_wrap.sv

@@ -16,12 +16,16 @@
 `include "vortex_afu.vh"
 
 module VX_afu_wrap #(
-	  parameter C_S_AXI_CTRL_ADDR_WIDTH = 8,
-	  parameter C_S_AXI_CTRL_DATA_WIDTH	= 32,
-	  parameter C_M_AXI_MEM_ID_WIDTH    = 32,
-	  parameter C_M_AXI_MEM_DATA_WIDTH  = 512,
-	  parameter C_M_AXI_MEM_ADDR_WIDTH  = 25,
-      parameter C_M_AXI_MEM_NUM_BANKS   = 2
+	parameter C_S_AXI_CTRL_ADDR_WIDTH = 8,
+	parameter C_S_AXI_CTRL_DATA_WIDTH = 32,
+	parameter C_M_AXI_MEM_ID_WIDTH    = `PLATFORM_MEMORY_ID_WIDTH,
+	parameter C_M_AXI_MEM_DATA_WIDTH  = `PLATFORM_MEMORY_DATA_SIZE * 8,
+	parameter C_M_AXI_MEM_ADDR_WIDTH  = 64,
+`ifdef PLATFORM_MERGED_MEMORY_INTERFACE
+	parameter C_M_AXI_MEM_NUM_BANKS   = 1
+`else
+	parameter C_M_AXI_MEM_NUM_BANKS   = `PLATFORM_MEMORY_NUM_BANKS
+`endif
 ) (
     // System signals
     input wire clk,
@@ -31,7 +35,7 @@ module VX_afu_wrap #(
 `ifdef PLATFORM_MERGED_MEMORY_INTERFACE
 	`REPEAT (1, GEN_AXI_MEM, REPEAT_COMMA),
 `else
-	`REPEAT (`PLATFORM_MEMORY_BANKS, GEN_AXI_MEM, REPEAT_COMMA),
+	`REPEAT (`PLATFORM_MEMORY_NUM_BANKS, GEN_AXI_MEM, REPEAT_COMMA),
 `endif
     // AXI4-Lite slave interface
     input  wire                                 s_axi_ctrl_awvalid,
@@ -58,11 +62,7 @@ module VX_afu_wrap #(
 
     output wire                                 interrupt
 );
-`ifdef PLATFORM_MERGED_MEMORY_INTERFACE
-	localparam M_AXI_MEM_ADDR_WIDTH = `PLATFORM_MEMORY_ADDR_WIDTH + $clog2(`PLATFORM_MEMORY_BANKS);
-`else
 	localparam M_AXI_MEM_ADDR_WIDTH = `PLATFORM_MEMORY_ADDR_WIDTH;
-`endif
 
 	typedef enum logic [1:0] {
 		STATE_IDLE = 0,
@@ -71,8 +71,8 @@ module VX_afu_wrap #(
 		STATE_DONE = 3
 	} state_e;
 
-	localparam PENDING_SIZEW = 12; // max outstanding requests size
-	localparam C_M_AXI_MEM_NUM_BANKS_SW = `CLOG2(C_M_AXI_MEM_NUM_BANKS+1);
+	localparam PENDING_WR_SIZEW    = 12; // max outstanding requests size
+	localparam NUM_MEM_BANKS_SIZEW = `CLOG2(C_M_AXI_MEM_NUM_BANKS+1);
 
 	wire                                 m_axi_mem_awvalid_a [C_M_AXI_MEM_NUM_BANKS];
     wire                                 m_axi_mem_awready_a [C_M_AXI_MEM_NUM_BANKS];
@@ -108,11 +108,11 @@ module VX_afu_wrap #(
 `ifdef PLATFORM_MERGED_MEMORY_INTERFACE
 	`REPEAT (1, AXI_MEM_TO_ARRAY, REPEAT_SEMICOLON);
 `else
-	`REPEAT (`PLATFORM_MEMORY_BANKS, AXI_MEM_TO_ARRAY, REPEAT_SEMICOLON);
+	`REPEAT (`PLATFORM_MEMORY_NUM_BANKS, AXI_MEM_TO_ARRAY, REPEAT_SEMICOLON);
 `endif
 
 	reg [`CLOG2(`RESET_DELAY+1)-1:0] vx_reset_ctr;
-	reg [PENDING_SIZEW-1:0] vx_pending_writes;
+	reg [PENDING_WR_SIZEW-1:0] vx_pending_writes;
 	reg vx_reset = 1; // asserted at initialization
 	wire vx_busy;
 
@@ -200,7 +200,7 @@ module VX_afu_wrap #(
 	end
 
 	wire [C_M_AXI_MEM_NUM_BANKS-1:0] m_axi_wr_req_fire, m_axi_wr_rsp_fire;
-	wire [C_M_AXI_MEM_NUM_BANKS_SW-1:0] cur_wr_reqs, cur_wr_rsps;
+	wire [NUM_MEM_BANKS_SIZEW-1:0] cur_wr_reqs, cur_wr_rsps;
 
 	for (genvar i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin : g_m_axi_wr_req_fire
 		VX_axi_write_ack axi_write_ack (
@@ -224,14 +224,14 @@ module VX_afu_wrap #(
 	`POP_COUNT(cur_wr_reqs, m_axi_wr_req_fire);
 	`POP_COUNT(cur_wr_rsps, m_axi_wr_rsp_fire);
 
-	wire signed [C_M_AXI_MEM_NUM_BANKS_SW:0] reqs_sub = (C_M_AXI_MEM_NUM_BANKS_SW+1)'(cur_wr_reqs) -
-	                                                     (C_M_AXI_MEM_NUM_BANKS_SW+1)'(cur_wr_rsps);
+	wire signed [NUM_MEM_BANKS_SIZEW:0] reqs_sub = (NUM_MEM_BANKS_SIZEW+1)'(cur_wr_reqs) -
+	                                                     (NUM_MEM_BANKS_SIZEW+1)'(cur_wr_rsps);
 
 	always @(posedge clk) begin
 		if (reset) begin
 			vx_pending_writes <= '0;
 		end else begin
-			vx_pending_writes <= vx_pending_writes + PENDING_SIZEW'(reqs_sub);
+			vx_pending_writes <= vx_pending_writes + PENDING_WR_SIZEW'(reqs_sub);
 		end
 	end
 
@@ -270,7 +270,7 @@ module VX_afu_wrap #(
 		.ap_ready       (ap_ready),
 		.ap_idle     	(ap_idle),
 		.interrupt 		(interrupt),
-		
+
 		.ap_ctrl_read   (ap_ctrl_read),
 
 	`ifdef SCOPE
@@ -287,9 +287,8 @@ module VX_afu_wrap #(
 	wire [M_AXI_MEM_ADDR_WIDTH-1:0] m_axi_mem_araddr_u [C_M_AXI_MEM_NUM_BANKS];
 
 	for (genvar i = 0; i < C_M_AXI_MEM_NUM_BANKS; ++i) begin : g_addressing
-		localparam [C_M_AXI_MEM_ADDR_WIDTH-1:0] BANK_OFFSET = C_M_AXI_MEM_ADDR_WIDTH'(`PLATFORM_MEMORY_OFFSET) + C_M_AXI_MEM_ADDR_WIDTH'(i) << M_AXI_MEM_ADDR_WIDTH;
-		assign m_axi_mem_awaddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_awaddr_u[i]) + BANK_OFFSET;
-		assign m_axi_mem_araddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_araddr_u[i]) + BANK_OFFSET;
+		assign m_axi_mem_awaddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_awaddr_u[i]) + C_M_AXI_MEM_ADDR_WIDTH'(`PLATFORM_MEMORY_OFFSET);
+		assign m_axi_mem_araddr_a[i] = C_M_AXI_MEM_ADDR_WIDTH'(m_axi_mem_araddr_u[i]) + C_M_AXI_MEM_ADDR_WIDTH'(`PLATFORM_MEMORY_OFFSET);
 	end
 
 	`SCOPE_IO_SWITCH (2);

hw/rtl/afu/xrt/vortex_afu.v

@@ -17,12 +17,12 @@ module vortex_afu #(
 	parameter C_S_AXI_CTRL_ADDR_WIDTH = 8,
 	parameter C_S_AXI_CTRL_DATA_WIDTH = 32,
 	parameter C_M_AXI_MEM_ID_WIDTH 	  = `PLATFORM_MEMORY_ID_WIDTH,
-	parameter C_M_AXI_MEM_DATA_WIDTH  = `PLATFORM_MEMORY_DATA_WIDTH,
+	parameter C_M_AXI_MEM_DATA_WIDTH  = (`PLATFORM_MEMORY_DATA_SIZE * 8),
 	parameter C_M_AXI_MEM_ADDR_WIDTH  = 64,
 `ifdef PLATFORM_MERGED_MEMORY_INTERFACE
     parameter C_M_AXI_MEM_NUM_BANKS   = 1
 `else
-    parameter C_M_AXI_MEM_NUM_BANKS   = `PLATFORM_MEMORY_BANKS
+    parameter C_M_AXI_MEM_NUM_BANKS   = `PLATFORM_MEMORY_NUM_BANKS
 `endif
 ) (
 	// System signals
@@ -33,7 +33,7 @@ module vortex_afu #(
 `ifdef PLATFORM_MERGED_MEMORY_INTERFACE
 	`REPEAT (1, GEN_AXI_MEM, REPEAT_COMMA),
 `else
-	`REPEAT (`PLATFORM_MEMORY_BANKS, GEN_AXI_MEM, REPEAT_COMMA),
+	`REPEAT (`PLATFORM_MEMORY_NUM_BANKS, GEN_AXI_MEM, REPEAT_COMMA),
 `endif
 
     // AXI4-Lite slave interface
@@ -75,7 +75,7 @@ module vortex_afu #(
 	`ifdef PLATFORM_MERGED_MEMORY_INTERFACE
 		`REPEAT (1, AXI_MEM_ARGS, REPEAT_COMMA),
 	`else
-		`REPEAT (`PLATFORM_MEMORY_BANKS, AXI_MEM_ARGS, REPEAT_COMMA),
+		`REPEAT (`PLATFORM_MEMORY_NUM_BANKS, AXI_MEM_ARGS, REPEAT_COMMA),
 	`endif
 		.s_axi_ctrl_awvalid (s_axi_ctrl_awvalid),
 		.s_axi_ctrl_awready (s_axi_ctrl_awready),
@@ -94,7 +94,7 @@ module vortex_afu #(
 		.s_axi_ctrl_rready  (s_axi_ctrl_rready),
 		.s_axi_ctrl_rdata   (s_axi_ctrl_rdata),
 		.s_axi_ctrl_rresp   (s_axi_ctrl_rresp),
-		
+
 		.s_axi_ctrl_bvalid  (s_axi_ctrl_bvalid),
 		.s_axi_ctrl_bready  (s_axi_ctrl_bready),
 		.s_axi_ctrl_bresp   (s_axi_ctrl_bresp),

hw/rtl/afu/xrt/vortex_afu.vh

@@ -14,18 +14,6 @@
 `ifndef VORTEX_AFU_VH
 `define VORTEX_AFU_VH
 
-`ifndef PLATFORM_MEMORY_BANKS
-`define PLATFORM_MEMORY_BANKS 2
-`endif
-
-`ifndef PLATFORM_MEMORY_ADDR_WIDTH
-`define PLATFORM_MEMORY_ADDR_WIDTH 31
-`endif
-
-`ifndef PLATFORM_MEMORY_DATA_WIDTH
-`define PLATFORM_MEMORY_DATA_WIDTH 512
-`endif
-
 `ifndef PLATFORM_MEMORY_OFFSET
 `define PLATFORM_MEMORY_OFFSET 0
 `endif

hw/rtl/libs/VX_async_ram_patch.sv

@@ -221,7 +221,7 @@ module VX_async_ram_patch #(
         VX_placeholder #(
             .O (1)
         ) placeholder2 (
-            .in  (),
+            .in  (1'b0),
             .out (is_raddr_reg)
         );
         wire [DATAW-1:0] rdata_a;

hw/rtl/libs/VX_axi_adapter.sv

@@ -251,7 +251,13 @@ module VX_axi_adapter #(
         // AXI write address channel
 
         assign m_axi_awvalid[i] = req_xbar_valid_out[i] && xbar_rw_out && ~m_axi_aw_ack;
-        assign m_axi_awaddr[i]  = ADDR_WIDTH_OUT'(xbar_addr_out) << LOG2_DATA_SIZE;
+
+    if (INTERLEAVE) begin : g_m_axi_awaddr_i
+        assign m_axi_awaddr[i]  = (ADDR_WIDTH_OUT'(xbar_addr_out) << (BANK_SEL_BITS + LOG2_DATA_SIZE)) | (ADDR_WIDTH_OUT'(i) << LOG2_DATA_SIZE);
+    end else begin : g_m_axi_awaddr_ni
+        assign m_axi_awaddr[i]  = (ADDR_WIDTH_OUT'(xbar_addr_out) << LOG2_DATA_SIZE) | (ADDR_WIDTH_OUT'(i) << (BANK_ADDR_WIDTH + LOG2_DATA_SIZE));
+    end
+
         assign m_axi_awid[i]    = TAG_WIDTH_OUT'(xbar_tag_out);
         assign m_axi_awlen[i]   = 8'b00000000;
         assign m_axi_awsize[i]  = 3'(LOG2_DATA_SIZE);
@@ -280,7 +286,13 @@ module VX_axi_adapter #(
         end
 
         assign m_axi_arvalid[i] = req_xbar_valid_out[i] && ~xbar_rw_out;
-        assign m_axi_araddr[i]  = ADDR_WIDTH_OUT'(xbar_addr_out) << LOG2_DATA_SIZE;
+
+        // convert address to byte-addressable space
+    if (INTERLEAVE) begin : g_m_axi_araddr_i
+        assign m_axi_araddr[i]  = (ADDR_WIDTH_OUT'(xbar_addr_out) << (BANK_SEL_BITS + LOG2_DATA_SIZE)) | (ADDR_WIDTH_OUT'(i) << LOG2_DATA_SIZE);
+    end else begin : g_m_axi_araddr_ni
+        assign m_axi_araddr[i]  = (ADDR_WIDTH_OUT'(xbar_addr_out) << LOG2_DATA_SIZE) | (ADDR_WIDTH_OUT'(i) << (BANK_ADDR_WIDTH + LOG2_DATA_SIZE));
+    end
         assign m_axi_arid[i]    = TAG_WIDTH_OUT'(xbar_tag_r_out);
         assign m_axi_arlen[i]   = 8'b00000000;
         assign m_axi_arsize[i]  = 3'(LOG2_DATA_SIZE);