revert "vunit/sim_if: Active-HDL supports VHDL 2019 (#755)"

This reverts commit 3aa1c05.

vunit/sim_if/activehdl.py

@@ -109,7 +109,7 @@ def _std_str(vhdl_standard):
         """
         Convert standard to format of Active-HDL command line flag
         """
-        if vhdl_standard <= VHDL.STD_2019:
+        if vhdl_standard <= VHDL.STD_2008:
             return f"-{vhdl_standard!s}"
 
         raise ValueError(f"Invalid VHDL standard {vhdl_standard!s}")