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ast: Add support for array-to-array assignment#5630

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widlarizer merged 1 commit intoYosysHQ:mainfrom
apullin:array-assignment
Mar 5, 2026
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ast: Add support for array-to-array assignment#5630
widlarizer merged 1 commit intoYosysHQ:mainfrom
apullin:array-assignment

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@apullin apullin commented Jan 23, 2026

This commit adds support for SystemVerilog array-to-array assignment operations that were previously unsupported:

  1. Direct array assignment: b = a;
  2. Array ternary expressions: out = sel ? a : b;

Both single-dimensional and multi-dimensional unpacked arrays are supported. The implementation expands these array operations during AST simplification into element-wise assignments.

Example of now-supported syntax:

wire [7:0] state_regs[8];
wire [7:0] r[8];
wire [7:0] sel[8];
assign sel = condition ? state_regs : r;

I was generating some verilog with Google XLS, and this pattern came up, and I found that it was not supported by Yosys.

Tests are added in tests/svtypes/array_assign.sv.

This collides with PR #2331, but that PR has been up for > 5 years. This implementation also addresses the review feedback from that PR, including support for array ternary expressions
(out = sel ? a : b) and multi-dimensional unpacked arrays.

@apullin apullin requested a review from widlarizer as a code owner January 23, 2026 14:50
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This looks okay to me, although I'm far from the expert on the Verilog frontend.

This approach will generate quite a lot of code if the arrays have large dimensions. Any thoughts on addressing that or (more likely) at least surfacing it as something other than OS resource exhaustion?

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apullin commented Jan 23, 2026

quite a lot

AFAIK, RTLIL just has to be a ton of entries, wires, ports - there's no bulk memory copy primitive, so combinational array assignment fundamentally requires N parallel paths.

But large code gen is an issue: arrays of ~100K elements take ~3s, and ~1M elements can take 60s+.

I added a warning for arrays over 10,000 elements.

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I'm happy with a warning, and I don't think you can do better here, either.

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apullin commented Mar 4, 2026

@widlarizer bump

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Otherwise looks good

This commit adds support for SystemVerilog array-to-array assignment
operations that were previously unsupported:

1. Direct array assignment: `b = a;`
2. Array ternary expressions: `out = sel ? a : b;`

Both single-dimensional and multi-dimensional unpacked arrays are
supported. The implementation expands these array operations during
AST simplification into element-wise assignments.

Example of now-supported syntax:
```systemverilog
wire [7:0] state_regs[8];
wire [7:0] r[8];
wire [7:0] sel[8];
assign sel = condition ? state_regs : r;
```

Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
@apullin apullin force-pushed the array-assignment branch from deadaa9 to 6ac8c8c Compare March 5, 2026 05:34
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apullin commented Mar 5, 2026

  • Added the requested test case. Sure enough, it failed. Resolved by mapping array assignment expansion by element position (range-direction aware), instead of reusing raw numeric indices across LHS/RHS.
  • Also added the procedural ternary array-assignment case.

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Looks good

@widlarizer widlarizer added this pull request to the merge queue Mar 5, 2026
Merged via the queue into YosysHQ:main with commit 629bf3d Mar 5, 2026
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apullin commented Mar 5, 2026

Yay. Can probably mark #2331 as superseded ?

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4 participants