ast: Add support for array-to-array assignment#5630
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whitequark
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This looks okay to me, although I'm far from the expert on the Verilog frontend.
This approach will generate quite a lot of code if the arrays have large dimensions. Any thoughts on addressing that or (more likely) at least surfacing it as something other than OS resource exhaustion?
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AFAIK, RTLIL just has to be a ton of entries, wires, ports - there's no bulk memory copy primitive, so combinational array assignment fundamentally requires N parallel paths. But large code gen is an issue: arrays of ~100K elements take ~3s, and ~1M elements can take 60s+. I added a warning for arrays over 10,000 elements. |
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I'm happy with a warning, and I don't think you can do better here, either. |
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@widlarizer bump |
widlarizer
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- Integrate this case as a test
- Cover the
// Wrap in AST_BLOCK for proceduralcase with a test
Otherwise looks good
This commit adds support for SystemVerilog array-to-array assignment operations that were previously unsupported: 1. Direct array assignment: `b = a;` 2. Array ternary expressions: `out = sel ? a : b;` Both single-dimensional and multi-dimensional unpacked arrays are supported. The implementation expands these array operations during AST simplification into element-wise assignments. Example of now-supported syntax: ```systemverilog wire [7:0] state_regs[8]; wire [7:0] r[8]; wire [7:0] sel[8]; assign sel = condition ? state_regs : r; ``` Co-Authored-By: Claude Opus 4.5 <noreply@anthropic.com>
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Yay. Can probably mark #2331 as superseded ? |
This commit adds support for SystemVerilog array-to-array assignment operations that were previously unsupported:
b = a;out = sel ? a : b;Both single-dimensional and multi-dimensional unpacked arrays are supported. The implementation expands these array operations during AST simplification into element-wise assignments.
Example of now-supported syntax:
I was generating some verilog with Google XLS, and this pattern came up, and I found that it was not supported by Yosys.
Tests are added in
tests/svtypes/array_assign.sv.This collides with PR #2331, but that PR has been up for > 5 years. This implementation also addresses the review feedback from that PR, including support for array ternary expressions
(
out = sel ? a : b) and multi-dimensional unpacked arrays.