chore(Boards,CMSIS,PeriphDrivers): Add fixes and features for MAX32572 to prep for release #890
Conversation
… RISCV applications since it was undefined.
…C. Removed GPIO2 and GPIO3.
…ded OTP in max32572.h.
…y files for ME55.
…oved GPIO2/GPIO3 from GCR registers.
…rors for RISCV applications since it was undefined." This reverts commit 176fe65.
…CTRL.chkres1 to bit 11.
…ield position and width.
|
/clang-format-run |
|
/clang-format-run |
|
/clang-format-run |
sihyung-maxim
changed the title
github-actions
bot
added
the
Tools
| #define MXC_BASE_INTR ((uint32_t)0xE5070000UL) | ||
| //#define MXC_BASE_INTR ((uint32_t)0xE5000000UL) | ||
| /* For MCUs with extra RISCV core (RISCV1) */ | ||
| #ifdef __riscv1 |
There was a problem hiding this comment.
Where does __riscv1 get defined?
There was a problem hiding this comment.
This isn't relevant for the ME55 but will be for the ME13B, so there are no __riscv1 references yet. This is preparation for ME13B since the ME55 is a subset of ME13B. Should I hold off on this change?
There was a problem hiding this comment.
Ok, yeah we might want to hold off until the system for the dual RISC-V cores is a little more fleshed out. We should be able to check against a generic RISC-V compilation as well as a specific core. So we may want to rename this to something like __core_riscv1 and define the base one as __core_riscv0. Right now our RISCV_CORE build option is just a toggle switch, but I can see it becoming a selector for the ME13B.
There was a problem hiding this comment.
Up to you. I'm fine either way since it's unused
Description
This PR syncs up the changes from the
dev/me13b_me55-examplesbranch to the latest design changes of the MAX32572Checklist Before Requesting Review