add test vpwl

ansys · Mar 4, 2024 · 76efb34 · 76efb34
1 parent 6206230
commit 76efb34
Showing 1 changed file with 11 additions and 0 deletions.
diff --git a/_unittest/test_21_Circuit.py b/_unittest/test_21_Circuit.py
@@ -809,3 +809,14 @@ def test_45_create_circuit_from_multizone_layout(self, add_edb):
         self.aedtapp.insert_design("test_45")
         self.aedtapp.connect_circuit_models_from_multi_zone_cutout(project_connexions, edb_zones, defined_ports)
         assert [mod for mod in list(self.aedtapp.modeler.schematic.components.values()) if "PagePort" in mod.name]
+
+    def test_46_create_vpwl(self):
+        myres = self.aedtapp.modeler.schematic.create_voltage_pwl(
+            compname="V1", time_list=[0, "1u"], voltage_list=[0, 1]
+        )
+        assert myres.refdes != ""
+        assert type(myres.id) is int
+        assert myres.parameters["time1"] == "0"
+        assert myres.parameters["time2"] == "1u"
+        assert myres.parameters["val1"] == "0"
+        assert myres.parameters["val2"] == "1"