Create circuit schematics

_unittest/example_models/T21/pcieg5_32gt.ami

@@ -0,0 +1,30 @@
+|******************************************************************************
+| Spec. AMI model generated by SPISim's BPro, Generated on 20170831143940
+|
+| IP of this model belongs to SPISim or its licensed BPro user.
+|*****************************************************************************
+(ANSYS_PCIeG5_32GT_RX
+   (Description "Example PCIeG5 Rx 32GT model")
+   (Reserved_Parameters
+      (AMI_Version (Usage Info) (Type String) (Value "6.1")         (Description "Supported AMI version"))
+      (Ignore_Bits (Usage Info) (Type Integer) (Default 500)          (Description "Ignore four bits to fill up tapped delay line."))
+      (Max_Init_Aggressors (Usage Info) (Type Integer) (Default 25) (Description "Number of aggressors is actually unlimited."))
+      (Init_Returns_Impulse (Usage Info) (Type Boolean)             (Default True) (Description "Both impulse and parameters_out returned."))
+      (Supporting_Files (Usage Info) (Type String) (Table ("PCIeG5_32GT.ens")) (Description "CTLE Performance table"))
+      (GetWave_Exists  (Usage Info) (Type Boolean) (Default True) (Description "GetWave is well and truly provided in the module."))
+   ) | End Reserved_Parameters
+
+   |****************************************************************************
+   | Remove or tamper LICENSE_INFO values will cause simulation being aborted!
+   |****************************************************************************
+   (Model_Specific
+      (LICENSE_INFO (Usage In) (Type String) (Default "LICENSED_ANSYS_AEDT_E168EFCC0268A84087F7B23B510CB41F") (Description "Licensing info."))
+      | ------------------ MAIN Settings ------------------
+      (MDL_SUB_MODS (Usage In) (Type String) (Default "CTLE,DFE") (Description "Cascaded stages"))
+      | ------------------ CTLE Settings ------------------
+      (MDL_IDX_FILE (Usage In) (Type String) (Default "PCIeG5_32GT.ens") (Description "Params index table"))
+      (MDL_IDX_VALU (Usage In) (Type String) (Default "-1") (Description "Params table rowID"))
+      (ADC (Usage In) (Type Integer) (Range -5 -15 -5) (Default -5) (Description "DC Gain in dB"))
+      |(CTLE_OUPT_FILE (Usage In) (Type String) (Default "C:/Temp/WorkSpace/SPISim/CST/PCIe/32GT/PCIeG5_32GT.csv") (Description "Output generated FD array for checking purpose"))      
+   ) | End Model_Specific
+) | End SPISim_SPEC_AMI

_unittest/example_models/T21/pcieg5_32gt.ibs

@@ -0,0 +1,100 @@
+|***************************************************************************
+|
+[IBIS Ver]      5.1
+[File name]     pcieg5_32gt.ibs
+[File rev]      1.00
+[Date]          Jan 1, 2017
+[Source]        BPro (http://www.spisim.com)
+[Copyright]     Copyright 2017 ~, SPISim LLC. All right reserved.
+|
+|***************************************************************************
+|
+[Component]     Spec_Model
+[Manufacturer]  SPISim LLC
+[Package]
+|               typ             min             max
+R_pkg           0.0             0.0             0.0
+L_pkg           0.0             0.0             0.0
+C_pkg           0.0             0.0             0.0
+|
+|***************************************************************************
+|
+[PIN]   signal_name     model_name      R_pin   L_pin   C_pin
+1p       TxP             Tx              NA     NA     NA
+1n       TxN             Tx              NA     NA     NA
+2p       RxP             Rx              NA     NA     NA
+2n       RxN             Rx              NA     NA     NA
+|
+|***************************************************************************
+|
+[Diff Pin] inv_pin  vdiff  tdelay_typ  tdelay_min  tdelay_max
+1p         1n       0.1V   NA          NA          NA
+2p         2n       0.1V   NA          NA          NA
+|
+|****************************************************************
+|
+[Model]     Rx
+Model_type  Input
+|
+C_comp 0.00p 0.00p 0.00p
+Vinh = 0.55
+Vinl = 0.45
+|
+[Temperature_Range]  25    100   0
+[Voltage Range]      1.2   1.14  1.26
+|
+| The IV table below is equivalent to 50 ohms single-ended load
+[GND Clamp]
+-6.6              -0.132            -0.132            -0.132
+ 0.0               0.0               0.0               0.0
+ 6.6               0.132             0.132             0.132
+
+[Power Clamp]
+-6.6               0.132e-9          0.132e-9          0.132e-9
+ 0.0               0.0               0.0               0.0
+ 6.6              -0.132e-9          -0.132e-9         -0.132e-9
+
+[Algorithmic Model]
+Executable Windows_VisualStudio_32 pcieg5_32gt_WIN32.dll pcieg5_32gt.ami
+Executable Windows_VisualStudio_64 pcieg5_32gt_WIN64.dll pcieg5_32gt.ami
+Executable Linux_gcc_64            pcieg5_32gt_LX64.so   pcieg5_32gt.ami
+[End Algorithmic Model]
+
+|
+|***************************************************************************
+|
+[Model]        Tx
+Model_type     Output
+Polarity       Non-Inverting
+Enable         Active-High
+|
+Vmeas =        0.55
+|                            typ                min                max
+C_comp                       0                  0                  0
+[Voltage Range]             1.1                 1.0                1.2
+[Temperature Range]         60                  100                0
+|
+|***************************************************************************
+|
+[Pulldown]
+-2.500 -5.00000E-02 -5.00000E-02 -5.00000E-02
+0.000  +0.00000E+00 +0.00000E+00 +0.00000E+00
+2.500  +5.00000E-02 +5.00000E-02 +5.00000E-02
+[Pullup]
+-2.500 +5.00000E-02 +5.00000E-02 +5.00000E-02
+0.000  +0.00000E+00 +0.00000E+00 +0.00000E+00
+2.500  -5.00000E-02 -5.00000E-02 -5.00000E-02
+|
+[Ramp]
+dV/dt_r 0.2796/15p    0.2610/23.5p    0.2976/13p
+dV/dt_f 0.2796/15p    0.2610/23.5p    0.2976/13p
+|
+|
+[Algorithmic Model]
+Executable Windows_VisualStudio_32 pcieg5_32gt_WIN32.dll pcieg5_32gt.ami
+Executable Windows_VisualStudio_64 pcieg5_32gt_WIN64.dll pcieg5_32gt.ami
+Executable Linux_gcc_64            pcieg5_32gt_LX64.so   pcieg5_32gt.ami
+[End Algorithmic Model]
+
+|***************************************************************************
+[End]

_unittest/test_21_Circuit.py

@@ -19,6 +19,7 @@
 netlist1 = "netlist_small.cir"
 netlist2 = "Schematic1.qcv"
 touchstone = "SSN_ssn.s6p"
+touchstone_custom = "SSN_custom.s6p"
 touchstone2 = "Galileo_V3P3S0.ts"
 ami_project = "AMI_Example"
 
@@ -834,3 +835,56 @@ def test_46_create_vpwl(self):
         # time and voltage different length
         myres = self.aedtapp.modeler.schematic.create_voltage_pwl(compname="V3", time_list=[0], voltage_list=[0, 1])
         assert myres is False
+
+    def test_47_automatic_lna(self):
+        touchstone_file = os.path.join(local_path, "example_models", test_subfolder, touchstone_custom)
+
+        status, diff_pairs, comm_pairs = self.aedtapp.create_lna_schematic_from_snp(
+            touchstone=touchstone_file,
+            start_frequency=0,
+            stop_frequency=70,
+            auto_assign_diff_pairs=True,
+            separation=".",
+            pattern=["component", "pin", "net"],
+            analyze=False,
+        )
+        assert status
+
+    def test_48_automatic_tdr(self):
+        touchstone_file = os.path.join(local_path, "example_models", test_subfolder, touchstone_custom)
+
+        result, tdr_probe_name = self.aedtapp.create_tdr_schematic_from_snp(
+            touchstone=touchstone_file,
+            probe_pins=["A-MII-RXD1_30.SQFP28X28_208.P"],
+            probe_ref_pins=["A-MII-RXD1_65.SQFP20X20_144.N"],
+            termination_pins=["A-MII-RXD2_32.SQFP28X28_208.P", "A-MII-RXD2_66.SQFP20X20_144.N"],
+            differential=True,
+            design_name="TDR",
+            rise_time=35,
+            use_convolution=True,
+            analyze=False,
+        )
+        assert result
+
+    def test_49_automatic_ami(self):
+        touchstone_file = os.path.join(local_path, "example_models", test_subfolder, touchstone_custom)
+        ami_file = os.path.join(local_path, "example_models", test_subfolder, "pcieg5_32gt.ibs")
+        result, eye_curve_tx, eye_curve_rx = self.aedtapp.create_ami_schematic_from_snp(
+            touchstone=touchstone_file,
+            ibis_ami=ami_file,
+            component_name="Spec_Model",
+            tx_buffer_name="1p",
+            rx_buffer_name="2p",
+            use_ibis_buffer=False,
+            differential=True,
+            tx_pins=["A-MII-RXD1_30.SQFP28X28_208.P"],
+            tx_refs=["A-MII-RXD1_65.SQFP20X20_144.N"],
+            rx_pins=["A-MII-RXD2_32.SQFP28X28_208.P"],
+            rx_refs=["A-MII-RXD2_66.SQFP20X20_144.N"],
+            bit_pattern="random_bit_count=2.5e3 random_seed=1",
+            unit_interval="31.25ps",
+            use_convolution=True,
+            analyze=False,
+            design_name="AMI",
+        )
+        assert result