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Refactor CSR
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Signed-off-by: Michal Czyz <[email protected]>
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@mczyz-antmicro
mczyz-antmicro committed Mar 8, 2024
1 parent a8e5b30 commit 19cea37
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Showing 2 changed files with 78 additions and 78 deletions.
16 changes: 8 additions & 8 deletions xls/modules/dma/common.x
View file
Original file line number Diff line number Diff line change
Expand Up @@ -17,10 +17,10 @@
pub struct TransferDescBundle<ADDR_W: u32> { address: uN[ADDR_W], length: uN[ADDR_W] }

pub struct MainCtrlBundle<ADDR_W: u32> {
startAddress: uN[ADDR_W],
lineCount: uN[ADDR_W],
lineLength: uN[ADDR_W],
lineStride: uN[ADDR_W],
start_address: uN[ADDR_W],
line_count: uN[ADDR_W],
line_length: uN[ADDR_W],
line_stride: uN[ADDR_W],
}

pub fn zeroTransferDescBundle<ADDR_W: u32>() -> TransferDescBundle {
Expand All @@ -29,9 +29,9 @@ pub fn zeroTransferDescBundle<ADDR_W: u32>() -> TransferDescBundle {

pub fn zeroMainCtrlBundle<ADDR_W: u32>() -> MainCtrlBundle {
MainCtrlBundle {
startAddress: uN[ADDR_W]:0,
lineCount: uN[ADDR_W]:0,
lineLength: uN[ADDR_W]:0,
lineStride: uN[ADDR_W]:0
start_address: uN[ADDR_W]:0,
line_count: uN[ADDR_W]:0,
line_length: uN[ADDR_W]:0,
line_stride: uN[ADDR_W]:0
}
}
140 changes: 70 additions & 70 deletions xls/modules/dma/csr.x
View file
Original file line number Diff line number Diff line change
Expand Up @@ -64,7 +64,7 @@ pub fn ptrace<DATA_W: u32, REGS_N: u32>(registers: uN[DATA_W][REGS_N]) -> () {
}

struct CsrState<DATA_W: u32, REGS_N: u32> {
registerFile: uN[DATA_W][REGS_N],
register_file: uN[DATA_W][REGS_N],
writer_sync: u1,
writer_wait: u1,
reader_sync: u1,
Expand Down Expand Up @@ -108,7 +108,7 @@ proc Csr<ADDR_W: u32, DATA_W: u32, REGS_N: u32> {

init {
(CsrState {
registerFile: uN[DATA_W][REGS_N]:[uN[DATA_W]:0, ...],
register_file: uN[DATA_W][REGS_N]:[uN[DATA_W]:0, ...],
writer_sync: u1:0,
reader_sync: u1:0,
writer_wait: u1:0,
Expand All @@ -117,7 +117,7 @@ proc Csr<ADDR_W: u32, DATA_W: u32, REGS_N: u32> {
}

next(tok: token, state: CsrState<DATA_W, REGS_N>) {
trace!(state.registerFile);
trace!(state.register_file);
trace!(state.writer_sync);
trace!(state.writer_wait);
trace!(state.reader_sync);
Expand All @@ -131,15 +131,15 @@ proc Csr<ADDR_W: u32, DATA_W: u32, REGS_N: u32> {
let (tok, write_req, write_req_valid) = recv_non_blocking(tok, write_req, zero_write_req);

// Handle read response
let read_value = state.registerFile[read_req.addr];
let read_value = state.register_file[read_req.addr];
let read_resp_value = ReadResp { data: read_value };
let tok = send_if(tok, read_resp, read_req_valid, read_resp_value);

// Handle write response
let next_register_file = if write_req_valid {
update(state.registerFile, write_req.addr, write_req.data)
update(state.register_file, write_req.addr, write_req.data)
} else {
state.registerFile
state.register_file
};
let tok = send_if(tok, write_resp, write_req_valid, WriteResp {});

Expand All @@ -151,15 +151,15 @@ proc Csr<ADDR_W: u32, DATA_W: u32, REGS_N: u32> {

let next_writer_sync = if writer_sync_valid { u1:1 } else { state.writer_sync };

let next_writer_wait = if state.registerFile[config::CONTROL_REGISTER][0:1] {
let next_writer_wait = if state.register_file[config::CONTROL_REGISTER][0:1] {
u1:1
} else {
state.writer_wait
};

// Writer: Transfer
let start_write_transfer = if state.registerFile[config::CONTROL_REGISTER][2:3] {
state.registerFile[config::CONTROL_REGISTER][0:1]
let start_write_transfer = if state.register_file[config::CONTROL_REGISTER][2:3] {
state.register_file[config::CONTROL_REGISTER][0:1]
} else {
state.writer_wait & state.writer_sync
};
Expand All @@ -173,10 +173,10 @@ proc Csr<ADDR_W: u32, DATA_W: u32, REGS_N: u32> {
// Writer: Transfer configuration
let tok = send(tok, ch_writer_start, start_write_transfer);
let writer_ctrl_bundle = MainCtrlBundle<ADDR_W> {
startAddress: state.registerFile[config::WRITER_START_ADDRESS] as uN[ADDR_W],
lineCount: state.registerFile[config::WRITER_LINE_LENGTH] as uN[ADDR_W],
lineLength: state.registerFile[config::WRITER_LINE_COUNT] as uN[ADDR_W],
lineStride: state.registerFile[config::WRITER_STRIDE_BETWEEN_LINES] as uN[ADDR_W]
start_address: state.register_file[config::WRITER_START_ADDRESS] as uN[ADDR_W],
line_count: state.register_file[config::WRITER_LINE_LENGTH] as uN[ADDR_W],
line_length: state.register_file[config::WRITER_LINE_COUNT] as uN[ADDR_W],
line_stride: state.register_file[config::WRITER_STRIDE_BETWEEN_LINES] as uN[ADDR_W]
};
let tok = send(tok, ch_writer_configuration, writer_ctrl_bundle);

Expand Down Expand Up @@ -209,15 +209,15 @@ proc Csr<ADDR_W: u32, DATA_W: u32, REGS_N: u32> {

let next_reader_sync = if reader_sync_valid { u1:1 } else { state.reader_sync };

let next_reader_wait = if state.registerFile[config::CONTROL_REGISTER][1:2] {
let next_reader_wait = if state.register_file[config::CONTROL_REGISTER][1:2] {
u1:1
} else {
state.reader_wait
};

// reader: Transfer
let start_read_transfer = if state.registerFile[config::CONTROL_REGISTER][3:4] {
state.registerFile[config::CONTROL_REGISTER][1:2]
let start_read_transfer = if state.register_file[config::CONTROL_REGISTER][3:4] {
state.register_file[config::CONTROL_REGISTER][1:2]
} else {
state.reader_wait & state.reader_sync
};
Expand All @@ -231,10 +231,10 @@ proc Csr<ADDR_W: u32, DATA_W: u32, REGS_N: u32> {
// Reader: Transfer configuration
let tok = send(tok, ch_reader_start, start_read_transfer);
let reader_ctrl_bundle = MainCtrlBundle<ADDR_W> {
startAddress: state.registerFile[config::READER_START_ADDRESS] as uN[ADDR_W],
lineCount: state.registerFile[config::READER_LINE_LENGTH] as uN[ADDR_W],
lineLength: state.registerFile[config::READER_LINE_COUNT] as uN[ADDR_W],
lineStride: state.registerFile[config::READER_STRIDE_BETWEEN_LINES] as uN[ADDR_W]
start_address: state.register_file[config::READER_START_ADDRESS] as uN[ADDR_W],
line_count: state.register_file[config::READER_LINE_LENGTH] as uN[ADDR_W],
line_length: state.register_file[config::READER_LINE_COUNT] as uN[ADDR_W],
line_stride: state.register_file[config::READER_STRIDE_BETWEEN_LINES] as uN[ADDR_W]
};
let tok = send(tok, ch_reader_configuration, reader_ctrl_bundle);

Expand Down Expand Up @@ -262,7 +262,7 @@ proc Csr<ADDR_W: u32, DATA_W: u32, REGS_N: u32> {
};

// Common: Clear start bit unless in loop-mode
let control_register = state.registerFile[config::CONTROL_REGISTER];
let control_register = state.register_file[config::CONTROL_REGISTER];
let is_writer_loop_mode = control_register[4:5];
let is_reader_loop_mode = control_register[5:6];
//
Expand All @@ -284,7 +284,7 @@ proc Csr<ADDR_W: u32, DATA_W: u32, REGS_N: u32> {

// State
CsrState {
registerFile: next_register_file,
register_file: next_register_file,
writer_sync: next_writer_sync,
reader_sync: next_reader_sync,
writer_wait: next_writer_wait,
Expand Down Expand Up @@ -466,21 +466,21 @@ proc TestLoopMode {
let state = if state == u32:0 {
// Prepare configs
let rw_config = MainCtrlBundle<TEST_ADDR_W> {
startAddress: u32:0x1000,
lineCount: u32:0x64,
lineLength: u32:0x01,
lineStride: u32:0x00
start_address: u32:0x1000,
line_count: u32:0x64,
line_length: u32:0x01,
line_stride: u32:0x00
};

let init_csr_values = AdrDatPair[u32:8]:[
(config::READER_START_ADDRESS, rw_config.startAddress),
(config::READER_LINE_LENGTH, rw_config.lineLength),
(config::READER_LINE_COUNT, rw_config.lineCount),
(config::READER_STRIDE_BETWEEN_LINES, rw_config.lineStride),
(config::WRITER_START_ADDRESS, rw_config.startAddress),
(config::WRITER_LINE_LENGTH, rw_config.lineLength),
(config::WRITER_LINE_COUNT, rw_config.lineCount),
(config::WRITER_STRIDE_BETWEEN_LINES, rw_config.lineStride),
(config::READER_START_ADDRESS, rw_config.start_address),
(config::READER_LINE_LENGTH, rw_config.line_length),
(config::READER_LINE_COUNT, rw_config.line_count),
(config::READER_STRIDE_BETWEEN_LINES, rw_config.line_stride),
(config::WRITER_START_ADDRESS, rw_config.start_address),
(config::WRITER_LINE_LENGTH, rw_config.line_length),
(config::WRITER_LINE_COUNT, rw_config.line_count),
(config::WRITER_STRIDE_BETWEEN_LINES, rw_config.line_stride),
];

for (i, tok): (u32, token) in u32:0..u32:8 {
Expand Down Expand Up @@ -666,21 +666,21 @@ proc TestLoopModeDisableSync {
let state = if state == u32:0 {
// Prepare configs
let rw_config = MainCtrlBundle<TEST_ADDR_W> {
startAddress: u32:0x1000,
lineCount: u32:0x64,
lineLength: u32:0x01,
lineStride: u32:0x00
start_address: u32:0x1000,
line_count: u32:0x64,
line_length: u32:0x01,
line_stride: u32:0x00
};

let init_csr_values = AdrDatPair[u32:8]:[
(config::READER_START_ADDRESS, rw_config.startAddress),
(config::READER_LINE_LENGTH, rw_config.lineLength),
(config::READER_LINE_COUNT, rw_config.lineCount),
(config::READER_STRIDE_BETWEEN_LINES, rw_config.lineStride),
(config::WRITER_START_ADDRESS, rw_config.startAddress),
(config::WRITER_LINE_LENGTH, rw_config.lineLength),
(config::WRITER_LINE_COUNT, rw_config.lineCount),
(config::WRITER_STRIDE_BETWEEN_LINES, rw_config.lineStride),
(config::READER_START_ADDRESS, rw_config.start_address),
(config::READER_LINE_LENGTH, rw_config.line_length),
(config::READER_LINE_COUNT, rw_config.line_count),
(config::READER_STRIDE_BETWEEN_LINES, rw_config.line_stride),
(config::WRITER_START_ADDRESS, rw_config.start_address),
(config::WRITER_LINE_LENGTH, rw_config.line_length),
(config::WRITER_LINE_COUNT, rw_config.line_count),
(config::WRITER_STRIDE_BETWEEN_LINES, rw_config.line_stride),
];

for (i, tok): (u32, token) in u32:0..u32:8 {
Expand Down Expand Up @@ -866,21 +866,21 @@ proc TestSingleMode {
let state = if state == u32:0 {
// Prepare configs
let rw_config = MainCtrlBundle<TEST_ADDR_W> {
startAddress: u32:0x1000,
lineCount: u32:0x64,
lineLength: u32:0x01,
lineStride: u32:0x00
start_address: u32:0x1000,
line_count: u32:0x64,
line_length: u32:0x01,
line_stride: u32:0x00
};

let init_csr_values = AdrDatPair[u32:8]:[
(config::READER_START_ADDRESS, rw_config.startAddress),
(config::READER_LINE_LENGTH, rw_config.lineLength),
(config::READER_LINE_COUNT, rw_config.lineCount),
(config::READER_STRIDE_BETWEEN_LINES, rw_config.lineStride),
(config::WRITER_START_ADDRESS, rw_config.startAddress),
(config::WRITER_LINE_LENGTH, rw_config.lineLength),
(config::WRITER_LINE_COUNT, rw_config.lineCount),
(config::WRITER_STRIDE_BETWEEN_LINES, rw_config.lineStride),
(config::READER_START_ADDRESS, rw_config.start_address),
(config::READER_LINE_LENGTH, rw_config.line_length),
(config::READER_LINE_COUNT, rw_config.line_count),
(config::READER_STRIDE_BETWEEN_LINES, rw_config.line_stride),
(config::WRITER_START_ADDRESS, rw_config.start_address),
(config::WRITER_LINE_LENGTH, rw_config.line_length),
(config::WRITER_LINE_COUNT, rw_config.line_count),
(config::WRITER_STRIDE_BETWEEN_LINES, rw_config.line_stride),
];

for (i, tok): (u32, token) in u32:0..u32:8 {
Expand Down Expand Up @@ -1069,21 +1069,21 @@ proc TestSingleModeDisableSync {
let state = if state == u32:0 {
// Prepare configs
let rw_config = MainCtrlBundle<TEST_ADDR_W> {
startAddress: u32:0x1000,
lineCount: u32:0x64,
lineLength: u32:0x01,
lineStride: u32:0x00
start_address: u32:0x1000,
line_count: u32:0x64,
line_length: u32:0x01,
line_stride: u32:0x00
};

let init_csr_values = AdrDatPair[u32:8]:[
(config::READER_START_ADDRESS, rw_config.startAddress),
(config::READER_LINE_LENGTH, rw_config.lineLength),
(config::READER_LINE_COUNT, rw_config.lineCount),
(config::READER_STRIDE_BETWEEN_LINES, rw_config.lineStride),
(config::WRITER_START_ADDRESS, rw_config.startAddress),
(config::WRITER_LINE_LENGTH, rw_config.lineLength),
(config::WRITER_LINE_COUNT, rw_config.lineCount),
(config::WRITER_STRIDE_BETWEEN_LINES, rw_config.lineStride),
(config::READER_START_ADDRESS, rw_config.start_address),
(config::READER_LINE_LENGTH, rw_config.line_length),
(config::READER_LINE_COUNT, rw_config.line_count),
(config::READER_STRIDE_BETWEEN_LINES, rw_config.line_stride),
(config::WRITER_START_ADDRESS, rw_config.start_address),
(config::WRITER_LINE_LENGTH, rw_config.line_length),
(config::WRITER_LINE_COUNT, rw_config.line_count),
(config::WRITER_STRIDE_BETWEEN_LINES, rw_config.line_stride),
];

for (i, tok): (u32, token) in u32:0..u32:8 {
Expand Down

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