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RELEASE_NOTES.md
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* 1 DDR controller implemented in the SH (always available)
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* 3 DDR controllers implemented in the CL (configurable number of implemented controllers allowed)
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-# Release 1.2.1
+# Release 1.2.2
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* Expanded [clock recipes](./hdk/docs/clock_recipes.csv)
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- * Virtual JTAG documentation updates
+ * Reduced DCP build times by 13% (34 mins) for cl_dram_dma example by adding an option to disable virtual jtag
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* Included encryption of .sv files for CL examples
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# Release 1.2.1
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