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@AWSwinefred AWSwinefred released this 19 Apr 19:28
· 169 commits to master since this release
v1.2.0
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Release 1.2.0

NOTE on Release 1.2.0

Release 1.2.0 is the first Generally Available release of the Shell, HDK, and SDK. This release provides F1 developers with documentation and tools to start building their Custom Logic (CL) designs to work with the F1 instances.

Any items in this release marked as WIP (Work-in-progress) or NA (Not available yet) are not currently supported by the 1.2.0 release.

Release 1.2.0 Content Overview

This is the first Generally Available release of the AWS EC2 FPGA Development Kit. Major updates are included for both the HDK and SDK directories. 1.2.0 a required version for all Developers running on F1 instances, and prior releases of the FPGA Development Kit are not supported.

All AFIs created with previous HDK versions will no longer correctly load on an F1 instance, hence a fpga-load-local-image command executed with an AFI created prior to 1.2.0 will return an error and not load.

Release 1.2.0 New Features Details

The following major features are included in this HDK release:

1. New Shell, with modified Shell/CL interface. Changes are covered in:

2. Integrated DMA in Beta Release. AWS Shell now includes DMA capabilities on behalf of the CL

  • The DMA bus toward the CL is multiplexed over sh_cl_dma_pcis AXI4 interface so the same address space can be accessed via DMA or directly via PCIe AppPF BAR4
  • DMA usage is covered in the new CL_DRAM_DMA example RTL verification/simulation and Software
  • A corresponding AWS Elastic DMA (EDMA) driver is provided.
  • EDMA Installation Readme provides installation and usage guidlines
  • The initial release supports a single queue in each direction
  • DMA support is in Beta stage with a known issue for DMA READ transactions that cross 4K address boundaries. See Kernel_Drivers_README for more information on restrictions for this release

3. CL User-defined interrupt events. The CL can now request sending MSI-X to the instance CPU

4. Added a Mandatory Manifest.txt file submitted with each DCP via create-fpga-image API

  • File content defined in AFI Manifest
  • AFI_Manifest.txt is created automatically if the developer is using the aws_build_dcp_from_cl.sh script
  • PCI Vendor ID and Device ID are part of the manifest
  • Shell Version is part of the manifest
  • The Manifest.txt file is required for AFI generation
  • All the examples and documentations for build include the description and dependency on the Manifest.txt

5. Decoupling Shell/CL interface clocking from the internal Shell Clock

  • All the Shell/CL interfaces running off clk_main_a0, and no longer required to be 250Mhz.
  • The default frequency using the HDK build flow for clk_main_a0 is 125Mhz as specified in recipe number A0. Allowing CL designs to have flexible frequency and not be constrained to 250Mhz only. All CL designs must include the recipe number in the manifest.txt file in order to generate an AFI.
  • All xdc scripts have been updated to clk_main_a0 and to reference a table with the possible clocks’ frequencies combinations
  • Updated CL_HELLO_WORLD and CL_DRAM_DMA examples to use the clk_main_a0

6. Additional User-defined Auxiliary Clocks

Additional tunable auxiliary clocks are generated by the Shell and fed to the CL. The clocks frequencies are set by choosing a clock recipe per group from a set of predefined frequencies combination in clock recipes table

  • Clock frequency selection is set during build time, and recorded in the manifest.txt (which should include the clock_recipe_a/b/c parameters)
  • Clock frequency programming in the FPGA slot itself occurs when the AFI is loaded. The list of supported frequencies is available here
  • See AWS_Shell_Interface_Specification for details on the clocking to the CL
  • See AFI Manifest for details on the AFI manifest data
  • xdc is automatically updated with the target frequency (WIP)

7. Additional PCIe BARs and update PCIe Physical Function mapping

** The AppPF now has 4 different PCIe BARs:**

  • BAR0 and BAR1 support 32-bit access for different memory ranges of the CL through separate AXI-L interfaces
  • BAR2 is used exclusively for the DMA inside the Shell and MSI-X interrupt tables
  • BAR4 expanded to 128GiB to cover all external DRAM memory space

** ManagementPF added additional PCIe BARs:**

** MgmtPF and AppPF are now represented as different PCIe devices in F1 instances:**

  • Each FPGA Slot will occupy two PCIe buses, one for AppPF and one for MgmtPF

8. Expanded AppPF BAR4 space to 128GiB

9. Added wider access on the Shell to CL AXI4 512-bit bus (sh_cl_dma_pcis)

  • Wider access provides higher bandwidth DMA and host to FPGA access
  • Instance CPU can now burst full 64-byte write burst to AppPF PCIe BAR4 if mapped as Burstable (a.k.a WC: WriteCombine) (WIP)
  • pci_poke_burst() and pci_poke64() calls were added to fpga_pci library to take advantage of this
  • CL_DRAM_DMA and CL_HELLO_WORLD examples support for a wider access was added

10. Support larger than 32-bit access to PCIe space

  • Large inbound transaction going to AppPF PCIe BAR4 will be passed onward to the CL
  • Large inbound transactions going to the other BARs will be split by the Shell to multiple 32-bit accesses, and satisfy AXI-L protocol specification.

11. Enhanced AXI4 error handling and reporting

  • Additional error conditions detected on the CL to Shell Interface and reported through fpga-describe-image tool
  • See AWS Shell Interface Specification for more details
  • FPGA Management Tool metrics output covers the additional error handling details

12. Expanded AXI ID space throughout the design

  • The AXI buses between Shell and CL support an expanded number of AXI ID bits to allow for bits to be added by AXI fabrics See AWS Shell Interface Specification for more details

13. Shell to CL interface metrics.

  • New metrics for monitoring the Shell to CL are available from the AFI Management Tools.
  • See fpga mgmt tools readme for more details

14. Virtual LED/DIP Switches.

  • Added CL capability to present virtual LEDs and push virtual DIP switches indications to the CL, set and read by FPGA Management Tools and without involving CL logic, providing the developer an environment similar to developing on local boards with LED and DIP switches
  • See new commands in FPGA Image Tools for description of the new functionality
  • CL_HELLO_WORLD example includes some logic to set LED and adjust according to vDIP
  • See AWS Shell Interface Specification for more details

15. Virtual JTAG

  • The Shell has the capability for supporting CL integrated Xilinx debug cores like Virtual I/O (VIO) and Integrated Logic Analyzer (ILA) and includes support for local/remote debug by running XVC
  • Virtual_JTAG_XVC describes how to use Virtual JTAG from linux shell
  • cl_debug_bridge module was added to HDK common directory
  • Support for generating .ltx files after create-fpga-image was added. .ltx file is required when running interactive ILA/VIO debug (WIP)
  • Build tcl and xdc includes the required changes to enable Virtual JTAG
  • See CL_DRAM_DMA for examples on using Virtual JTAG and XVC for debug

16. Examples summary table

17. Updated CL_HELLO_WORLD Example

  • Matching the new Shell/CL interface
  • Add support for 32-bit peek/poke via ocl_ AXI-L bus
  • Adding Virtual JTAG support with Xilinx ILA and VIO debug cores (WIP)
  • Demonstrate the use of Virtual LED and Virtual DIPSwitch
  • Runtime software examples, leveraging fpga_pci and fpga_mgmt C-libraries
  • Updated PCIe Vendor ID and Device ID
  • See CL HELLO WORLD readme for more details

18. Added CL_DRAM_DMA Example

  • Mapping AppPF PCIe BAR4 to DRAM
  • Using DMA to access same DRAM
  • Using SystemVerilog Bus constructs to simplify the code
  • Demonstrate the use of User interrupts
  • Demonstrate the use of bar1_ AXI-L bus
  • Includes Runtime C-code application under CL_DRAM_DMA software (WIP)
  • See CL_DRAM_DMA README

19. Software Programmer View document

20. Two C-libraries for FPGA PCIe access and for FPGA Management

  • The C-libraries are simplifying and adding more protections from developer’s mistakes when writing a runtime C-application
  • Fpga_mgmt.h cover the APIs for calling management functions
  • Fpga_pcie.h covers the API for access the various PCI memory spaces of the FPGA
  • CL_HELLO_WORLD and CL_DRAM_DMA examples updated to use these libraries.

21. VHDL support is added

  • Included Vivado encryption key file for VHDL
  • Added VHDL-specific line in encrypt.tcl reference files
  • Developer would need to add read_vhdl in create_dcp_from_cl.tcl

22. Additional FPGA Management Tools added

23. Support for Vivado 2017.1 Build

  • The FPGA Development AMI includes Vivado 2017.1
  • Older Vivado versions will not be supported

24. Embed the HDK version and Shell Version as part of git tree

25. Initial Release of SDAccel and OpenCL Support (NA)

  • Updated documentation in /sdk/SDAccel (NA)
  • OpenCL runtime HAL for supporting SDAccel and OpenCL ICD in /sdk/userspace (NA)
  • SDAccel build post-processing to register SDAccel xcl.bin as AFI. (NA)

26. Simplify handling of unused Shell to CL interfaces

  • Developers can simply call `include "unused_BUS_NAME_template.inc" for every unused interface
  • List of potential files to include is available in $HDK_SHELL_DIR/design/interfaces/unused\*
  • cl_hello_world.sv and cl_dram_dma.sv provide examples (at the each of each file)

27. Support multiple Vivado versions

  • hdk_setup.sh compares between the list of Vivado versions supported by the HDK and the installed vivado versions
  • hdk_setup.sh would automatically choose the Vivado version from the available binaries in AWS FPGA Developer's AMI

28. Changes in DRAM controller setting to improve bandwidth utilization

  • Change address decoding to ROW_COL_INTLV mode
  • Enable auto precharge on COL A3
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