Add demo DUT.

bittide · Feb 7, 2025 · 4543925 · 4543925
1 parent 1861263
commit 4543925
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diff --git a/.github/synthesis/debug.json b/.github/synthesis/debug.json
@@ -0,0 +1,3 @@
+[
+  {"top": "demoTest", "stage": "test"}
+]
diff --git a/bittide-instances/bittide-instances.cabal b/bittide-instances/bittide-instances.cabal
@@ -110,6 +110,9 @@ common common-options
     ghc-typelits-knownnat,
     ghc-typelits-natnormalise,
     lift-type,
+    lifted-base,
+    monad-control,
+    mtl,
     network-simple,
     pretty-simple,
     process,
@@ -137,7 +140,9 @@ library
     Bittide.Instances.Domains
     Bittide.Instances.Hacks
     Bittide.Instances.Hitl.BoardTest
+    Bittide.Instances.Hitl.Demo
     Bittide.Instances.Hitl.DnaOverSerial
+    Bittide.Instances.Hitl.Driver.Demo
     Bittide.Instances.Hitl.Driver.DnaOverSerial
     Bittide.Instances.Hitl.Driver.SwCcTopologies
     Bittide.Instances.Hitl.Driver.VexRiscv

diff --git a/bittide-instances/data/constraints/demoTest.xdc b/bittide-instances/data/constraints/demoTest.xdc
@@ -0,0 +1,44 @@
+# SPDX-FileCopyrightText: 2025 Google LLC
+#
+# SPDX-License-Identifier: Apache-2.0
+
+set_property BOARD_PART_PIN sysclk_125_n [get_ports SYSCLK_125_n]
+set_property BOARD_PART_PIN sysclk_125_p [get_ports SYSCLK_125_p]
+set_property BOARD_PART_PIN sma_mgt_refclk_n [get_ports SMA_MGT_REFCLK_C_n]
+set_property BOARD_PART_PIN sma_mgt_refclk_p [get_ports SMA_MGT_REFCLK_C_p]
+
+set_property BOARD_PART_PIN GPIO_LED_0_LS [get_ports spiDone]
+
+set_clock_groups \
+  -asynchronous \
+  -group [get_clocks -include_generated_clocks {SYSCLK_125_p}] \
+  -group [get_clocks -include_generated_clocks {SMA_MGT_REFCLK_C_p}]
+
+# Color   | FPGA pin      | LVLSHFT       | Connection
+# --------|---------------|---------------|------------------
+# Grey    | PMOD0_0       | IO1           | SYNC_OUT (legacy)
+# Blue    | PMOD0_1       | IO2           | FINC
+# Yellow  | PMOD0_2       | IO3           | MOSI/SDIO
+# Red     | PMOD0_3       | IO4           | SCLK
+# White   | PMOD0_4       | IO5           | SYNC_IN (legacy)
+# Purple  | PMOD0_5       | IO6           | FDEC
+# Green   | PMOD0_6       | IO7           | CSB
+# Orange  | PMOD0_7       | IO8           | MISO/SDO
+# Black   | Not connected | Not connected |
+# Brown   | PMOD_GND      | GND           | GND (SPI)
+
+# PMOD1_[0..7]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AN21} [get_ports {FINC}]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AH18} [get_ports {MOSI}]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AM19} [get_ports {SCLK}]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AF25} [get_ports {FDEC}]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AE21} [get_ports {CSB}]
+set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AM17} [get_ports {MISO}]
+
+# PMOD0_3
+# set_property -dict {IOSTANDARD LVCMOS12 PACKAGE_PIN AM19} [get_ports {shared_reset_btn}]
+
+# USER SMA GPIO_P
+set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN H27} [get_ports {SYNC_IN}]
+# USER_SMA_GPIO_N (connected on node 0 to SYNC_IN of all nodes)
+set_property -dict {IOSTANDARD LVCMOS18 PACKAGE_PIN G27} [get_ports {SYNC_OUT}]
diff --git a/bittide-instances/data/openocd/start.sh b/bittide-instances/data/openocd/start.sh
@@ -17,6 +17,6 @@ mkdir -p "${stderr_dir}"
 OPENOCD_STDERR_LOG="$(realpath ${OPENOCD_STDERR_LOG})"
 
 cd $(dirname $0)
-exec openocd-vexriscv -f ports.tcl -f sipeed.tcl -f vexriscv_init.tcl $@ \
+exec openocd-vexriscv $@ \
   > >(tee "${OPENOCD_STDOUT_LOG}") \
   2> >(tee "${OPENOCD_STDERR_LOG}" >&2)
diff --git a/bittide-instances/data/openocd/vexriscv-2chain.tcl b/bittide-instances/data/openocd/vexriscv-2chain.tcl
@@ -0,0 +1,48 @@
+-- SPDX-FileCopyrightText: 2025 Google LLC
+--
+-- SPDX-License-Identifier: Apache-2.0
+set user_gdb_port_a [env DEV_A_GDB]
+if { $user_gdb_port_a == "" } {
+  error "Required environment variable 'DEV_A_GDB' not set."
+}
+
+set user_gdb_port_b [env DEV_B_GDB]
+if { $user_gdb_port_b == "" } {
+  error "Required environment variable 'DEV_B_GDB' not set."
+}
+
+set git_top_level [string trim [exec git rev-parse --show-toplevel]]
+
+set _ENDIAN little
+set _TAP_TYPE 1234
+
+bindto 0.0.0.0
+
+if { [info exists CPUTAPID] } {
+  set _CPUTAPID $CPUTAPID
+} else {
+  set _CPUTAPID 0x10001fff
+}
+
+set _CHIPNAME vexrisc_ocd
+
+jtag newtap $_CHIPNAME chain0 -expected-id $_CPUTAPID -irlen 4 -ircapture 0x1 -irmask 0x0F
+jtag newtap $_CHIPNAME chain1 -expected-id $_CPUTAPID -irlen 4 -ircapture 0x1 -irmask 0x03
+
+target create $_CHIPNAME.cpu1 vexriscv -endian $_ENDIAN -chain-position $_CHIPNAME.bridge1 -gdb-port $user_gdb_port_b
+vexriscv readWaitCycles 10
+vexriscv cpuConfigFile [file join $git_top_level clash-vexriscv clash-vexriscv example-cpu ExampleCpu.yaml]
+
+target create $_CHIPNAME.cpu0 vexriscv -endian $_ENDIAN -chain-position $_CHIPNAME.bridge0 -gdb-port $user_gdb_port_a
+vexriscv readWaitCycles 10
+vexriscv cpuConfigFile [file join $git_top_level clash-vexriscv clash-vexriscv example-cpu ExampleCpu.yaml]
+
+poll_period 50
+
+init
+
+echo "Halting processor"
+
+halt
+
+sleep 1000