Dont use records for ilaPlotSetup arguments

bittide · Feb 7, 2025 · a0c291f · a0c291f
1 parent 24e1afe
commit a0c291f
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Showing 2 changed files with 13 additions and 23 deletions.
diff --git a/bittide-instances/src/Bittide/Instances/Hitl/IlaPlot.hs b/bittide-instances/src/Bittide/Instances/Hitl/IlaPlot.hs
@@ -27,7 +27,6 @@ module Bittide.Instances.Hitl.IlaPlot (
   -- * Interface Types
   CaptureCondition (..),
   isScheduledCaptureCondition,
-  IlaPlotSetup (..),
   IlaControl (..),
   PlotData (..),
   RfStageChange (..),
@@ -204,23 +203,6 @@ isScheduledCaptureCondition = \case
   UntilTrigger -> False
   DataChange -> False
 
-{- | All signals, as they are required for using clock control with
-ILA plotting capabilities.
--}
-data IlaPlotSetup dom = IlaPlotSetup
-  { sysClk :: Clock dom
-  -- ^ The stable system clock.
-  , sysRst :: Reset dom
-  -- ^ The system's reset line.
-  , allReady :: Signal dom Bool
-  -- ^ A boolean signal indicating that all transceivers are ready. See
-  -- 'Bittide.Transceiver.Output.linkReady'.
-  , startTest :: Signal dom Bool
-  -- ^ The test start signal coming from the HITLT VIO interface.
-  , syncIn :: Signal dom Bool
-  -- ^ The signal connected to @SYNC_IN@.
-  }
-
 {- | All signals, as they are required by the ILA trigger and capture
 conditions. You must use 'ilaPlotSetup' for generating them.
 -}
@@ -267,10 +249,19 @@ ilaPlotSetup ::
   forall dom.
   (HasCallStack) =>
   (HasDefinedInitialValues dom, HasSynchronousReset dom) =>
-  -- | required input signals
-  IlaPlotSetup dom ->
+  -- | The stable system clock.
+  Clock dom ->
+  -- | The system's reset line.
+  Reset dom ->
+  -- | A boolean signal indicating that all transceivers are ready. See
+  -- 'Bittide.Transceiver.Output.linkReady'.
+  Signal dom Bool ->
+  -- | The test start signal coming from the HITLT VIO interface.
+  Signal dom Bool ->
+  -- | The signal connected to @SYNC_IN@.
+  Signal dom Bool ->
   IlaControl dom
-ilaPlotSetup IlaPlotSetup{..} = IlaControl{..}
+ilaPlotSetup sysClk sysRst allReady startTest syncIn = IlaControl{..}
  where
   -- 'syncOutGenerator' is used to drive 'SYNC_OUT'.
   syncOut =

diff --git a/bittide-instances/src/Bittide/Instances/Hitl/SwCcTopologies.hs b/bittide-instances/src/Bittide/Instances/Hitl/SwCcTopologies.hs
@@ -64,7 +64,6 @@ import Bittide.Transceiver (transceiverPrbsN)
 import Bittide.Hitl
 import Bittide.Instances.Hitl.IlaPlot (
   IlaControl (..),
-  IlaPlotSetup (..),
   clockControlIla,
   ilaPlotSetup,
  )
@@ -764,7 +763,7 @@ swCcTopologyTest refClkDiff sysClkDiff syncIn rxns rxps miso jtagIn =
  where
   refClk = ibufds_gte3 refClkDiff :: Clock Ext200
   (sysClk, sysRst) = clockWizardDifferential sysClkDiff noReset
-  ilaControl@IlaControl{..} = ilaPlotSetup IlaPlotSetup{..}
+  ilaControl@IlaControl{..} = ilaPlotSetup sysClk tbReset allReady startTest syncIn
   startTest = isJust <$> testConfig
 
   testCounter =