Remove prog en

.github/synthesis/debug.json

@@ -0,0 +1,3 @@
+[
+  {"top": "swCcOneTopologyTest",           "stage": "test"}
+]

bittide-instances/src/Bittide/Instances/Hitl/Driver/SwCcTopologies.hs

@@ -33,8 +33,8 @@ import System.Timeout (timeout)
 
 import qualified Data.List as L
 
-getProbeProgEnTcl :: String
-getProbeProgEnTcl = getTestProbeTcl "*vioHitlt/probe_prog_en"
+getProbeTestbenchResetTcl :: String
+getProbeTestbenchResetTcl = getTestProbeTcl "*vioHitlt/probe_tb_reset"
 
 data TestStatus = TestRunning | TestDone Bool | TestTimeout deriving (Eq)
 
@@ -65,12 +65,17 @@ driverFunc testName targets = do
           error $ "Timeout while performing action: " <> actionName
         Just r -> pure r
 
-    initHwTargets :: VivadoM ()
-    initHwTargets = forM_ targets $ \(hwT, d) -> do
-      liftIO $ putStrLn $ "Preparing hardware target " <> show d.deviceId
+    deassertTbReset :: (HwTarget, DeviceInfo) -> VivadoM ()
+    deassertTbReset (hwT, d) = do
+      liftIO $ putStrLn $ "Deasserting testbench reset for " <> show d.deviceId
+      openHardwareTarget hwT
+      updateVio "vioHitlt" [("probe_tb_reset", "0")]
 
+    assertTbReset :: (HwTarget, DeviceInfo) -> VivadoM ()
+    assertTbReset (hwT, d) = do
+      liftIO $ putStrLn $ "Asserting testbench reset for " <> show d.deviceId
       openHardwareTarget hwT
-      updateVio "vioHitlt" [("probe_prog_en", "1")]
+      updateVio "vioHitlt" [("probe_tb_reset", "1")]
 
     initOpenOcd :: (a, DeviceInfo) -> Int -> IO ((Int, ProcessStdIoHandles), IO ())
     initOpenOcd (_, d) targetIndex = do
@@ -121,11 +126,7 @@ driverFunc testName targets = do
       liftIO $ putStrLn $ "Asserting test probe on " <> show d.deviceId
 
       openHardwareTarget hwT
-      updateVio
-        "vioHitlt"
-        [ ("probe_prog_en", "0")
-        , ("probe_test_start", "1")
-        ]
+      updateVio "vioHitlt" [("probe_test_start", "1")]
 
     getTestsStatus :: [(HwTarget, DeviceInfo)] -> [TestStatus] -> VivadoM [TestStatus]
     getTestsStatus [] _ = return []
@@ -177,18 +178,25 @@ driverFunc testName targets = do
         $ if code == ExitSuccess
           then (count + 1, acc)
           else (count, code)
-
-  initHwTargets
+  forM_ targets assertTbReset
+  forM_ targets deassertTbReset
+  -- Brings ilasetup out of reset
+  -- Ilasetup ensures that the SYN pulses are generated
+  -- Ilasetup brings SPI out of reset
+  -- Clock board is programmed
+  -- Domain starts running
+  -- Internal logic is brought out of reset
+  forM_ targets waitForSpiDone
+
+  -- Asserting start test starts captures
+  -- Delay counter prevents clock modifications
+  -- Once delay counter reaches maxbound clock control is running
   let gdbPorts = L.take (L.length targets) [3333 ..]
-  brackets (liftIO <$> L.zipWith initOpenOcd targets [0 ..]) (liftIO . snd) $ \_initOcdsData -> do
+  exitCodes <- brackets (liftIO <$> L.zipWith initOpenOcd targets [0 ..]) (liftIO . snd) $ \_initOcdsData -> do
     brackets (liftIO <$> L.zipWith initGdb gdbPorts targets) (liftIO . snd) $ \initGdbsData -> do
       let gdbs = fmap fst initGdbsData
       liftIO $ mapM_ ((errorToException =<<) . Gdb.loadBinary) gdbs
 
-      -- TODO: Replace `prog_en` vio with `enable_sync_gen` vio
-      mapM_
-        (\(hwT, _) -> openHardwareTarget hwT >> updateVio "vioHitlt" [("probe_prog_en", "0")])
-        targets
       -- liftIO $ mapM_ ((errorToException =<<) . Gdb.compareSections) gdbs
       liftIO $ mapM_ Gdb.continue gdbs
       mapM_ startTest targets
@@ -200,5 +208,23 @@ driverFunc testName targets = do
         $ putStrLn [i|Test case #{testName} passed on #{count} of #{L.length targets} targets|]
 
       return exitCode
+  pure exitCodes
  where
   testTimeoutMs = 60_000 :: Integer
+
+-- | Polls the `probe_spi_done` probe of `vioHitlt` untill it becomes "1"
+waitForSpiDone :: (HwTarget, DeviceInfo) -> VivadoM ()
+waitForSpiDone target@(hwT, d) = do
+  openHardwareTarget hwT
+  [(probeName, spiDone)] <- readVio "vioHitlt" ["probe_spi_done"]
+  liftIO
+    $ putStrLn
+    $ "On target "
+    <> show d.deviceId
+    <> " Read probe "
+    <> probeName
+    <> ": "
+    <> spiDone
+  if spiDone == "1"
+    then pure ()
+    else waitForSpiDone target

bittide-instances/src/Bittide/Instances/Hitl/IlaPlot.hs

@@ -27,15 +27,14 @@ module Bittide.Instances.Hitl.IlaPlot (
   -- * Interface Types
   CaptureCondition (..),
   isScheduledCaptureCondition,
-  IlaPlotSetup (..),
   IlaControl (..),
   PlotData (..),
   RfStageChange (..),
 
   -- * ILA Plot
   ilaProbeNames,
   ilaPlotSetup,
-  callistoClockControlWithIla,
+  clockControlIla,
 
   -- * Helpers
   SyncPulseCycles,
@@ -69,7 +68,6 @@ import Clash.Cores.Xilinx.Xpm.Cdc.Gray (xpmCdcGray)
 import Clash.Cores.Xilinx.Xpm.Cdc.Single (xpmCdcSingle)
 import Clash.Explicit.Reset.Extra
 
-import Clash.Signal (HiddenClockResetEnable, withClockResetEnable)
 import Control.Arrow (second, (***))
 import Data.Bool (bool)
 import Data.Constraint.Nat.Extra (
@@ -205,23 +203,6 @@ isScheduledCaptureCondition = \case
   UntilTrigger -> False
   DataChange -> False
 
-{- | All signals, as they are required for using clock control with
-ILA plotting capabilities.
--}
-data IlaPlotSetup dom = IlaPlotSetup
-  { sysClk :: Clock dom
-  -- ^ The stable system clock.
-  , sysRst :: Reset dom
-  -- ^ The system's reset line.
-  , allReady :: Signal dom Bool
-  -- ^ A boolean signal indicating that all transceivers are ready. See
-  -- 'Bittide.Transceiver.Output.linkReady'.
-  , startTest :: Signal dom Bool
-  -- ^ The test start signal coming from the HITLT VIO interface.
-  , syncIn :: Signal dom Bool
-  -- ^ The signal connected to @SYNC_IN@.
-  }
-
 {- | All signals, as they are required by the ILA trigger and capture
 conditions. You must use 'ilaPlotSetup' for generating them.
 -}
@@ -268,10 +249,19 @@ ilaPlotSetup ::
   forall dom.
   (HasCallStack) =>
   (HasDefinedInitialValues dom, HasSynchronousReset dom) =>
-  -- | required input signals
-  IlaPlotSetup dom ->
+  -- | The stable system clock.
+  Clock dom ->
+  -- | The system's reset line.
+  Reset dom ->
+  -- | A boolean signal indicating that all transceivers are ready. See
+  -- 'Bittide.Transceiver.Output.linkReady'.
+  Signal dom Bool ->
+  -- | The test start signal coming from the HITLT VIO interface.
+  Signal dom Bool ->
+  -- | The signal connected to @SYNC_IN@.
+  Signal dom Bool ->
   IlaControl dom
-ilaPlotSetup IlaPlotSetup{..} = IlaControl{..}
+ilaPlotSetup sysClk sysRst allReady startTest syncIn = IlaControl{..}
  where
   -- 'syncOutGenerator' is used to drive 'SYNC_OUT'.
   syncOut =
@@ -455,21 +445,14 @@ data DiffResult a
     TooLarge
   deriving (Generic, BitPack, NFDataX, Functor, Eq, Ord, Show)
 
-type CallistoCc n m sys cfg =
-  (HiddenClockResetEnable sys, HasSynchronousReset sys) =>
-  cfg ->
-  Signal sys (BitVector n) ->
-  Vec n (Signal sys (RelDataCount m)) ->
-  Signal sys (CallistoResult n)
-
-{-# NOINLINE callistoClockControlWithIla #-}
+{-# NOINLINE clockControlIla #-}
 
 {- | Wrapper on 'Bittide.ClockControl.Callisto.callistoClockControl'
 additionally dumping all the data that is required for producing
 plots of the clock control behavior.
 -}
-callistoClockControlWithIla ::
-  forall n m cfg sys dyn.
+clockControlIla ::
+  forall n m sys dyn.
   (HasCallStack) =>
   (KnownDomain dyn, KnownDomain sys, HasSynchronousReset sys) =>
   (KnownNat n, KnownNat m) =>
@@ -488,24 +471,21 @@ callistoClockControlWithIla ::
   Clock dyn ->
   Clock sys ->
   Reset sys ->
-  cfg ->
-  CallistoCc n m sys cfg ->
+  Signal sys (CallistoResult n) ->
   -- | Ila trigger and capture conditions
   IlaControl sys ->
   -- | Link availability mask
   Signal sys (BitVector n) ->
   -- | Statistics provided by elastic buffers.
   Vec n (Signal sys (RelDataCount m)) ->
-  Signal sys (CallistoResult n)
-callistoClockControlWithIla dynClk clk rst callistoCfg callistoCc IlaControl{..} mask ebs =
-  hwSeqX ilaInstance (muteDuringCalibration <$> calibrating <*> output)
+  Signal sys Bool
+clockControlIla dynClk clk rst callistoResult IlaControl{..} mask ebs =
+  hwSeqX ilaInstance calibrating
  where
-  output = withClockResetEnable clk rst enableGen $ callistoCc callistoCfg mask ebs
-
   -- Condense multicycle speedchange outputs into a single cycle for the ILA
-  mscChanging = isRising clk rst enableGen False (isJust . maybeSpeedChange <$> output)
-  newMsc = mux mscChanging (maybeSpeedChange <$> output) (pure Nothing)
-  callistoOutputIla = (\record field -> record{maybeSpeedChange = field}) <$> output <*> newMsc
+  mscChanging = isRising clk rst enableGen False (isJust . maybeSpeedChange <$> callistoResult)
+  newMsc = mux mscChanging (maybeSpeedChange <$> callistoResult) (pure Nothing)
+  callistoOutputIla = (\record field -> record{maybeSpeedChange = field}) <$> callistoResult <*> newMsc
 
   filterCounts vMask vCounts = flip map (zip vMask vCounts)
     $ \(isActive, count) -> if isActive == high then count else 0
@@ -604,12 +584,6 @@ callistoClockControlWithIla dynClk clk rst callistoCfg callistoCc IlaControl{..}
         (minBound :: Index 3)
         scheduledCapture
 
-  -- do not forward clock modifications during calibration
-  muteDuringCalibration active ccResult =
-    ccResult
-      { maybeSpeedChange = bool (maybeSpeedChange ccResult) Nothing active
-      }
-
   -- Note that we always need to capture everything before the trigger
   -- fires, because the data that the ILA captures is undefined
   -- otherwise. Moreover, @syncStart@ does not hold at the trigger,
@@ -646,7 +620,7 @@ callistoClockControlWithIla dynClk clk rst callistoCfg callistoCc IlaControl{..}
   ilaInstance =
     setName @"ilaPlot"
       $ ila
-        (ilaConfig ilaProbeNames){depth = D16384, stages = 2}
+        (ilaConfig ilaProbeNames){depth = D16384, stages = 3}
         -- the ILA must run on a stable clock
         clk
         -- trigger as soon as we start