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Merge pull request #30 from chili-chips-ba/issue#9
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Updated i2c part according to issue
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@chili-chips-ba
chili-chips-ba authored Nov 6, 2024
2 parents 8d67c78 + 3c69f4b commit a259e9e
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Showing 5 changed files with 194 additions and 28 deletions.
35 changes: 31 additions & 4 deletions 1.hw/lib/ip/i2c_master/i2c_ctrl.sv
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Expand Up @@ -55,7 +55,9 @@ module i2c_ctrl (
input logic scl_di,

output logic sda_oe,
input logic sda_di
input logic sda_di,

input logic [7:0] pause_duration
);

typedef enum logic [3:0] {
Expand All @@ -67,7 +69,8 @@ module i2c_ctrl (
WRITE_REG_ADDR = 4'd5,
WRITE_REG_DATA = 4'd6,
STOP = 4'd7,
RESTART = 4'd8
RESTART = 4'd8,
WAIT = 4'd9
} state_t;

state_t state;
Expand All @@ -79,6 +82,8 @@ module i2c_ctrl (
logic [3:0] bit_cnt, bit_cnt_dec;
logic post_serial_data;
logic acknowledge_bit;
logic [7:0] outer_counter;
logic [8:0] inner_counter;

assign bit_cnt_dec = 4'(bit_cnt - 4'd1);

Expand All @@ -97,6 +102,8 @@ module i2c_ctrl (
acknowledge_bit <= 1'b0;
scl_do <= 1'b1;
sda_do <= 1'b1;
outer_counter <= '0;
inner_counter <= '0;
end
else begin
`ifndef ICARUS
Expand All @@ -112,9 +119,9 @@ module i2c_ctrl (
slave_address_plus_rw <= {slave_address, 1'b0};
scl_do <= 1'b1;
sda_do <= 1'b1;
register_done <= 1'b0;

if (enable == 1'b1) begin
register_done <= 1'b0;
state <= START;
post_state <= WRITE_SLAVE_ADDR;
end
Expand Down Expand Up @@ -333,11 +340,31 @@ module i2c_ctrl (
register_done <= 1'b1;
end
2'd3: begin
state <= IDLE;
outer_counter <= pause_duration;
inner_counter <= 9'd400;
process_cnt <= 2'd0;
register_done <= 1'b0;
state <= WAIT;
end
endcase
end

//----------------------
WAIT: if (strobe_400kHz == 1'b1) begin
scl_do <= 1'b1;
sda_do <= 1'b1;
if (outer_counter > 8'd0) begin
if (inner_counter > 9'd0) begin
inner_counter <= 9'(inner_counter - 9'(1));
end else begin
inner_counter <= 9'd400;
outer_counter <= 8'(outer_counter - 8'(1));
end
end else begin
state <= IDLE;
end
end

//----------------------
RESTART: if (strobe_400kHz == 1'b1) begin
unique case (process_cnt)
Expand Down
65 changes: 65 additions & 0 deletions 1.hw/lib/ip/i2c_master/i2c_init_IMX219.mem
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56 changes: 56 additions & 0 deletions 1.hw/lib/ip/i2c_master/i2c_init_IMX283.mem
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47 changes: 33 additions & 14 deletions 1.hw/lib/ip/i2c_master/i2c_top.sv
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Expand Up @@ -42,8 +42,9 @@
// - for most part operates in sync with external 400kHz strobe
//========================================================================

import top_pkg::*;
module i2c_top #(
parameter I2C_SLAVE_ADDR = 7'd16
parameter I2C_SLAVE_ADDR = 7'd26
)(

//clocks and resets
Expand All @@ -53,20 +54,24 @@ module i2c_top #(

//I/O pads
inout wire i2c_scl,
inout wire i2c_sda
inout wire i2c_sda,

//Misc/Debug
output bus8_t debug_pins
);


parameter NUM_REGISTERS = 56;

//--------------------------------
// I2C Master
//--------------------------------
logic i2c_enable;

logic [15:0] i2c_reg_addr;
logic [6:0] i2c_reg_cnt;
logic [5:0] i2c_reg_cnt;
logic i2c_reg_done;

logic [23:0] i2c_data_init[65];
logic [31:0] i2c_data_init[NUM_REGISTERS];
logic [7:0] i2c_data_in;

logic i2c_scl_do;
Expand All @@ -76,6 +81,8 @@ module i2c_top #(
logic i2c_sda_do;
logic i2c_sda_di;
logic i2c_sda_oe;

logic [7:0] i2c_pause;

i2c_ctrl u_ctrl (
.clk (clk), //i
Expand All @@ -92,13 +99,13 @@ module i2c_top #(
.scl_di (i2c_scl_di), //i

.sda_oe (i2c_sda_oe), //o
.sda_di (i2c_sda_di) //i

.sda_di (i2c_sda_di), //i
.pause_duration (i2c_pause) //i[7:0]
);


`ifndef SIM_ONLY
initial $readmemh("i2c_init.mem", i2c_data_init);
initial $readmemh("i2c_init_IMX283.mem", i2c_data_init);

`else
string i2c_init_mem_file;
Expand All @@ -108,23 +115,24 @@ module i2c_top #(
$readmemh(i2c_init_mem_file, i2c_data_init);
end
else begin
$readmemh("../../../1.hw/lib/ip/i2c_master/i2c_init.mem", i2c_data_init);
$readmemh("../../../1.hw/lib/ip/i2c_master/i2c_init_IMX283.mem", i2c_data_init);
end
end
`endif

assign i2c_enable = (i2c_reg_cnt < 7'd65);
assign i2c_reg_addr = i2c_data_init[i2c_reg_cnt][23:8];
assign i2c_data_in = i2c_data_init[i2c_reg_cnt][7:0];
assign i2c_enable = (i2c_reg_cnt < NUM_REGISTERS);
assign i2c_reg_addr = i2c_data_init[i2c_reg_cnt][31:16];
assign i2c_data_in = i2c_data_init[i2c_reg_cnt][15:8];
assign i2c_pause = i2c_data_init[i2c_reg_cnt][7:0];

always_ff @(negedge areset_n or posedge clk) begin
if (areset_n == 1'b0) begin
i2c_reg_cnt <= '0;
end
else if ({strobe_400kHz, i2c_enable} == 2'b11) begin
if (i2c_reg_done == 1'd1) begin
if (i2c_reg_cnt < 7'd65) begin
i2c_reg_cnt <= 7'(i2c_reg_cnt + 7'd1);
if (i2c_reg_cnt < NUM_REGISTERS) begin
i2c_reg_cnt <= 6'(i2c_reg_cnt + 6'd1);
end
end
end
Expand All @@ -142,6 +150,17 @@ module i2c_top #(
.I ({ 1'b0, 1'b0 }), //i
.T ({ ~i2c_sda_oe, ~i2c_scl_oe }) //i: 3-state enable: 1=input, 0=output
);

assign debug_pins = {
i2c_sda_di,
i2c_scl_di,
i2c_sda_oe,
i2c_scl_oe,
i2c_enable,
areset_n,
i2c_reg_done,
strobe_400kHz
};

endmodule: i2c_top

Expand Down
19 changes: 9 additions & 10 deletions 2.sim/cocotb/top/i2c.gtkw
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@@ -1,41 +1,40 @@
[*]
[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
[*] Wed Jun 5 21:41:45 2024
[*] Fri Oct 25 09:34:30 2024
[*]
[dumpfile] "/mnt/c/Users/Armin/Desktop/openeye/2.sim/cocotb/top/sim_build/top.fst"
[dumpfile_mtime] "Wed Jun 5 21:20:43 2024"
[dumpfile_size] 11807435
[dumpfile_mtime] "Fri Oct 25 09:33:45 2024"
[dumpfile_size] 785597
[savefile] "/mnt/c/Users/Armin/Desktop/openeye/2.sim/cocotb/top/i2c.gtkw"
[timestart] 0
[size] 1588 827
[pos] 32767 32767
[size] 1000 600
[pos] -1 -1
*-28.586885 2054290000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[sst_width] 214
[signals_width] 238
[sst_expanded] 1
[sst_vpaned_height] 488
[sst_vpaned_height] 319
@200
-top
@28
top.u_i2c.areset_n
top.u_i2c.strobe_400kHz
@200
-top/u_i2c
@420
top.u_i2c.I2C_SLAVE_ADDR
@22
top.u_i2c.i2c_data_in[7:0]
top.u_i2c.i2c_reg_addr[15:0]
@28
top.u_i2c.i2c_read_write
top.u_i2c.i2c_scl
top.u_i2c.i2c_scl_di
top.u_i2c.i2c_scl_do
top.u_i2c.i2c_sda
top.u_i2c.i2c_sda_di
top.u_i2c.i2c_sda_do
top.u_i2c.i2c_enable
@23
top.u_i2c.i2c_reg_cnt[6:0]
top.u_i2c.i2c_pause[7:0]
@200
-top/u_i2c/u_ctrl
@28
Expand Down

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