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Pull requests: chipsalliance/caliptra-rtl

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Pull requests list

AES test cases
#725 opened Feb 5, 2025 by Nitsirks Loading…
fixed hmac drbg
#723 opened Feb 4, 2025 by mojtaba-bisheh Loading…
1
@mojtaba-bisheh
Fix comment typo
#719 opened Jan 31, 2025 by flaviens Loading…
1
Fix comment typo
#718 opened Jan 31, 2025 by flaviens Loading…
1
Integration spec updates
#713 opened Jan 28, 2025 by Nitsirks • Draft
2
[aes] Connect EDN interface
#700 opened Jan 20, 2025 by vogelpi Loading…
6
Publish HTML docs for 1.1 RTL in addition to main
#676 opened Dec 23, 2024 by jhand2 Loading…
10
[DOCS] Document some paranoia checks in release checklist
#656 opened Dec 6, 2024 by calebofearth • Draft
DELETE THIS -- TEST PR -- User/anjpar/caliptra ss fuse ctrl
#607 opened Oct 23, 2024 by nileshbpat • Draft
1
Add coverage report
#587 opened Sep 10, 2024 by kiryk Loading…
2
Integration docs: Add recommended TRNG self-test thresholds.
#569 opened Aug 13, 2024 by korran Loading…
Add test for JTAG during uC reset
#554 opened Jul 4, 2024 by robertszczepanski Loading…
Patch 1.0 RTL with Lint Fixes enhancement New feature or request
#518 opened May 17, 2024 by calebofearth Loading…
@calebofearth
9
libs: ahb_slv_sif: Latch hsize on address phase Future
#502 opened Apr 17, 2024 by wkkuna Loading…
3
Fix PC setup after waking from clock gating in Verilator Future
#380 opened Jan 16, 2024 by robertszczepanski Loading…
12
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