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Merge pull request #1001 from chipsalliance/veer-el2 #158

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Merge pull request #1001 from chipsalliance/veer-el2

Merge pull request #1001 from chipsalliance/veer-el2 #158

Run time

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Job Run time
generate-config
4s
build-spike / Build Spike
7m 32s
generate-code (riscv_arithmetic_basic_test, uvm)
3m 26s
generate-code (riscv_rand_instr_test, uvm)
3m 31s
generate-code (riscv_jump_stress_test, uvm)
3m 23s
generate-code (riscv_loop_test, uvm)
3m 31s
generate-code (riscv_rand_jump_test, uvm)
3m 20s
generate-code (riscv_mmu_stress_test, uvm)
3m 28s
generate-code (riscv_no_fence_test, uvm)
3m 28s
generate-code (riscv_illegal_instr_test, uvm)
3m 24s
generate-code (riscv_ebreak_test, uvm)
3m 28s
generate-code (riscv_ebreak_debug_mode_test, uvm)
3m 23s
generate-code (riscv_full_interrupt_test, uvm)
3m 28s
generate-code (riscv_unaligned_load_store_test, uvm)
3m 22s
generate-code (riscv_non_compressed_instr_test, uvm)
3m 16s
generate-code (riscv_hint_instr_test, uvm)
3m 24s
generate-code (riscv_pmp_test, uvm)
3m 26s
generate-code (riscv_arithmetic_basic_test, pyflow)
4m 21s
run-tests (riscv_arithmetic_basic_test, uvm)
58s
run-tests (riscv_rand_instr_test, uvm)
1m 0s
run-tests (riscv_jump_stress_test, uvm)
57s
run-tests (riscv_loop_test, uvm)
1m 14s
run-tests (riscv_rand_jump_test, uvm)
58s
run-tests (riscv_mmu_stress_test, uvm)
2m 0s
run-tests (riscv_no_fence_test, uvm)
1m 13s
run-tests (riscv_illegal_instr_test, uvm)
59s
run-tests (riscv_ebreak_test, uvm)
57s
run-tests (riscv_ebreak_debug_mode_test, uvm)
58s
run-tests (riscv_full_interrupt_test, uvm)
1m 6s
run-tests (riscv_unaligned_load_store_test, uvm)
57s
run-tests (riscv_non_compressed_instr_test, uvm)
1m 8s
run-tests (riscv_hint_instr_test, uvm)
1m 13s
run-tests (riscv_pmp_test, uvm)
55s
run-tests (riscv_arithmetic_basic_test, pyflow)
1m 7s
1h 20m 55s