workflows: Update RISCV toolchain & add 'Z' ext

Some of the 'I' ext instructions were once moved to separate Zicsr and Zifencei extensions. For newer toolchains the 'Z' extensions need to be explicitly requested in '-march'. Signed-off-by: Wiktoria Kuna <[email protected]>
chipsalliance · Feb 6, 2025 · e79b8d1 · e79b8d1
1 parent cef6f2a
commit e79b8d1
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Showing 2 changed files with 21 additions and 14 deletions.
diff --git a/.github/workflows/run-tests.yml b/.github/workflows/run-tests.yml
@@ -119,7 +119,14 @@ jobs:
       - uses: actions/checkout@v4
 
       - name: Install dependencies
-        run: sudo apt-get -qqy update && sudo apt-get -qqy install gcc-riscv64-unknown-elf device-tree-compiler
+        run: sudo apt-get -qqy update && sudo apt-get -qqy install device-tree-compiler
+
+      - name: Install cross-compiler
+        shell: bash
+        run: |
+          echo "deb http://archive.ubuntu.com/ubuntu/ noble main universe" | sudo tee -a /etc/apt/sources.list > /dev/null
+          sudo apt -qqy update && sudo apt -qqy --no-install-recommends install gcc-riscv64-unknown-elf
+          riscv64-unknown-elf-gcc --version
 
       - name: Setup python
         # python dependencies cannot be properly downloaded with new versions of python

diff --git a/run.py b/run.py
@@ -827,7 +827,7 @@ def parse_args(cwd):
                             command is not specified")
     parser.add_argument("--isa", type=str, default="",
                         help="RISC-V ISA subset")
-    parser.add_argument("--priv", type=str, default="",
+    parser.add_argument("--priv", type=str, default="m",
                         help="RISC-V privilege modes enabled in simulation [su]")
     parser.add_argument("-m", "--mabi", type=str, default="",
                         help="mabi used for compilation", dest="mabi")
@@ -951,40 +951,40 @@ def load_config(args, cwd):
             args.core_setting_dir = cwd + "/target/" + args.target
         if args.target == "rv32imc":
             args.mabi = "ilp32"
-            args.isa = "rv32imc"
+            args.isa = "rv32imc_zicsr_zifencei"
         elif args.target == "rv32imafdc":
             args.mabi = "ilp32"
-            args.isa = "rv32imafdc"
+            args.isa = "rv32imafdc_zicsr_zifencei"
         elif args.target == "rv32imc_sv32":
             args.mabi = "ilp32"
-            args.isa = "rv32imc"
+            args.isa = "rv32imc_zicsr_zifencei"
         elif args.target == "multi_harts":
             args.mabi = "ilp32"
-            args.isa = "rv32gc"
+            args.isa = "rv32gc_zicsr_zifencei"
         elif args.target == "rv32imcb":
             args.mabi = "ilp32"
-            args.isa = "rv32imcb"
+            args.isa = "rv32imcb_zicsr_zifencei"
         elif args.target == "rv32i":
             args.mabi = "ilp32"
-            args.isa = "rv32i"
+            args.isa = "rv32i_zicsr_zifencei"
         elif args.target == "rv64imc":
             args.mabi = "lp64"
-            args.isa = "rv64imc"
+            args.isa = "rv64imc_zicsr_zifencei"
         elif args.target == "rv64imcb":
             args.mabi = "lp64"
-            args.isa = "rv64imcb"
+            args.isa = "rv64imcb_zicsr_zifencei"
         elif args.target == "rv64gc":
             args.mabi = "lp64"
-            args.isa = "rv64gc"
+            args.isa = "rv64gc_zicsr_zifencei"
         elif args.target == "rv64gcv":
             args.mabi = "lp64"
-            args.isa = "rv64gcv"
+            args.isa = "rv64gcv_zicsr_zifencei"
         elif args.target == "ml":
             args.mabi = "lp64"
-            args.isa = "rv64imc"
+            args.isa = "rv64imc_zicsr_zifencei"
         elif args.target == "rv64imafdc":
             args.mabi = "lp64"
-            args.isa = "rv64imafdc"
+            args.isa = "rv64imafdc_zicsr_zifencei"
         else:
             sys.exit("Unsupported pre-defined target: {}".format(args.target))
     else: