Merge pull request #1002 from chipsalliance/72580-update-ci

workflows: Update upload-artifacts to v4
chipsalliance · Feb 7, 2025 · fb6181b · fb6181b
2 parents 2c319b8 + 4bf494f
commit fb6181b
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Showing 3 changed files with 33 additions and 22 deletions.
diff --git a/.github/workflows/build-spike.yml b/.github/workflows/build-spike.yml
@@ -36,7 +36,7 @@ jobs:
           key: ${{ env.cache_name }}_${{ env.cache_date }}
           restore-keys: ${{ env.cache_name }}_
 
-      - name: Install prerequisities
+      - name: Install prerequisites
         if: ${{ steps.cache.outputs.cache-hit != 'true' }}
         run: |
           sudo apt -qqy update && sudo apt -qqy --no-install-recommends install \

diff --git a/.github/workflows/run-tests.yml b/.github/workflows/run-tests.yml
@@ -22,12 +22,14 @@ jobs:
         name: Prepare test types
         run: |
           python3 -m pip install pyyaml
-          echo "tests=$(python3 .github/scripts/parse_testlist.py $RISCV_TARGET)" | tee -a $GITHUB_OUTPUT
+          python3 .github/scripts/parse_testlist.py $RISCV_TARGET > tests.list
+          echo "tests=$(cat tests.list)" | tee -a $GITHUB_OUTPUT
       - id: hash
         name: Prepare files' hash
         run: |
-          echo "files-hash=$(sha256sum **/*.sv **/*.py **/*.yml **/*.yaml | cut -d\  -f1 | sha256sum | cut -d\  -f1)" | tee -a $GITHUB_OUTPUT
-          
+          sha256sum **/*.sv **/*.py **/*.yaml > file.hash
+          echo "files-hash=$(cat file.hash | cut -d\  -f1 | sha256sum | cut -d\  -f1)" | tee -a $GITHUB_OUTPUT
+
 
   generate-code:
     runs-on: [ self-hosted, Linux, X64, gcp-custom-runners ]
@@ -39,7 +41,7 @@ jobs:
         test: ${{ fromJSON(needs.generate-config.outputs.test-types) }}
         version: [ uvm ]
         include:
-          - test: riscv_arithmetic_basic_test 
+          - test: riscv_arithmetic_basic_test
             version: pyflow
     env:
       GHA_EXTERNAL_DISK: additional-tools
@@ -89,9 +91,10 @@ jobs:
             --isa $RISCV_TARGET --mabi ilp32 --steps gen -v -o test 2>&1 | tee test/generate.log
 
       - name: Upload Artifacts
-        uses: actions/upload-artifact@v3
+        uses: actions/upload-artifact@v4
         if: always()
         with:
+          name: generate_code_${{ matrix.test }}_${{ matrix.version }}
           path: |
             test/asm_test/*.S
 
@@ -116,7 +119,14 @@ jobs:
       - uses: actions/checkout@v4
 
       - name: Install dependencies
-        run: sudo apt-get -qqy update && sudo apt-get -qqy install gcc-riscv64-unknown-elf device-tree-compiler
+        run: sudo apt-get -qqy update && sudo apt-get -qqy install device-tree-compiler
+
+      - name: Install cross-compiler
+        shell: bash
+        run: |
+          echo "deb http://archive.ubuntu.com/ubuntu/ noble main universe" | sudo tee -a /etc/apt/sources.list > /dev/null
+          sudo apt -qqy update && sudo apt -qqy --no-install-recommends install gcc-riscv64-unknown-elf
+          riscv64-unknown-elf-gcc --version
 
       - name: Setup python
         # python dependencies cannot be properly downloaded with new versions of python
@@ -174,9 +184,10 @@ jobs:
             --isa $RISCV_TARGET --mabi ilp32 --steps gcc_compile,iss_sim -v -o test 2>&1 | tee -a test/generate.log
 
       - name: Upload Artifacts
-        uses: actions/upload-artifact@v3
+        uses: actions/upload-artifact@v4
         if: always()
         with:
+          name: run_tests_log_${{ matrix.test }}_${{ matrix.version }}
           path: |
-            test/asm_test/*.log
             test/*.log
+            test/**/${{ matrix.test }}*.log
diff --git a/run.py b/run.py
@@ -827,7 +827,7 @@ def parse_args(cwd):
                             command is not specified")
     parser.add_argument("--isa", type=str, default="",
                         help="RISC-V ISA subset")
-    parser.add_argument("--priv", type=str, default="",
+    parser.add_argument("--priv", type=str, default="m",
                         help="RISC-V privilege modes enabled in simulation [su]")
     parser.add_argument("-m", "--mabi", type=str, default="",
                         help="mabi used for compilation", dest="mabi")
@@ -951,40 +951,40 @@ def load_config(args, cwd):
             args.core_setting_dir = cwd + "/target/" + args.target
         if args.target == "rv32imc":
             args.mabi = "ilp32"
-            args.isa = "rv32imc"
+            args.isa = "rv32imc_zicsr_zifencei"
         elif args.target == "rv32imafdc":
             args.mabi = "ilp32"
-            args.isa = "rv32imafdc"
+            args.isa = "rv32imafdc_zicsr_zifencei"
         elif args.target == "rv32imc_sv32":
             args.mabi = "ilp32"
-            args.isa = "rv32imc"
+            args.isa = "rv32imc_zicsr_zifencei"
         elif args.target == "multi_harts":
             args.mabi = "ilp32"
-            args.isa = "rv32gc"
+            args.isa = "rv32gc_zicsr_zifencei"
         elif args.target == "rv32imcb":
             args.mabi = "ilp32"
-            args.isa = "rv32imcb"
+            args.isa = "rv32imcb_zicsr_zifencei"
         elif args.target == "rv32i":
             args.mabi = "ilp32"
-            args.isa = "rv32i"
+            args.isa = "rv32i_zicsr_zifencei"
         elif args.target == "rv64imc":
             args.mabi = "lp64"
-            args.isa = "rv64imc"
+            args.isa = "rv64imc_zicsr_zifencei"
         elif args.target == "rv64imcb":
             args.mabi = "lp64"
-            args.isa = "rv64imcb"
+            args.isa = "rv64imcb_zicsr_zifencei"
         elif args.target == "rv64gc":
             args.mabi = "lp64"
-            args.isa = "rv64gc"
+            args.isa = "rv64gc_zicsr_zifencei"
         elif args.target == "rv64gcv":
             args.mabi = "lp64"
-            args.isa = "rv64gcv"
+            args.isa = "rv64gcv_zicsr_zifencei"
         elif args.target == "ml":
             args.mabi = "lp64"
-            args.isa = "rv64imc"
+            args.isa = "rv64imc_zicsr_zifencei"
         elif args.target == "rv64imafdc":
             args.mabi = "lp64"
-            args.isa = "rv64imafdc"
+            args.isa = "rv64imafdc_zicsr_zifencei"
         else:
             sys.exit("Unsupported pre-defined target: {}".format(args.target))
     else: