added is_lhs

Signed-off-by: Lukasz Dalek <[email protected]>
chipsalliance · Mar 22, 2021 · 2ca7f18 · 2ca7f18
1 parent 43169ff
commit 2ca7f18
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Showing 4 changed files with 8 additions and 2 deletions.
diff --git a/verilog/analysis/checkers/forbid_implicit_declarations_rule.cc b/verilog/analysis/checkers/forbid_implicit_declarations_rule.cc
@@ -74,8 +74,8 @@ void ForbidImplicitDeclarationsRule::Lint(const verible::TextStructureView& text
         for (const auto& itr : node.Value().local_references_to_bind) {
           ABSL_DIE_IF_NULL(itr.LastLeaf())->ApplyPreOrder(
               [&violations, &text_structure](const ReferenceComponent& node) {
-                if ((node.resolved_symbol == nullptr) ||  // Unresolved
-                    (node.identifier.begin() < node.resolved_symbol->Key()->begin())) {  // Implicit
+                if ((node.resolved_symbol == nullptr && node.is_lhs) ||  // Unresolved
+                    (node.resolved_symbol && (node.identifier.begin() < node.resolved_symbol->Key()->begin()))) {  // Implicit
                   const auto& contents = text_structure.Contents();
                   const auto offset = std::distance(contents.begin(),
                                                     node.identifier.begin());

diff --git a/verilog/analysis/symbol_table.cc b/verilog/analysis/symbol_table.cc
@@ -626,10 +626,13 @@ class SymbolTable::Builder : public TreeContextVisitor {
     // reference.
     DependentReferences& ref(reference_builders_.top());
 
+    const bool is_lhs = Context().IsInside(NodeEnum::kLPValue);
+
     const ReferenceComponent new_ref{
         .identifier = text,
         .ref_type = InferReferenceType(),
         .required_metatype = InferMetaType(),
+        .is_lhs = is_lhs,
     };
 
     // For instances' named ports, and types' named parameters,

diff --git a/verilog/analysis/symbol_table.h b/verilog/analysis/symbol_table.h
@@ -130,6 +130,8 @@ struct ReferenceComponent {
   // TODO: privatize this member.
   const SymbolTableNode* resolved_symbol = nullptr;
 
+  bool is_lhs = false;
+
  public:
   ReferenceComponent(const ReferenceComponent&) = default;  // safe to copy
   ReferenceComponent(ReferenceComponent&&) = default;

diff --git a/verilog/tools/lint/testdata/long_line.sv b/verilog/tools/lint/testdata/long_line.sv
@@ -1,4 +1,5 @@
 module long_line;
+wire aaaaaaaaaaaaaaaaaaa;
 initial begin
   aaaaaaaaaaaaaaaaaaa[12341234] <= cccccccccccccccccccccccc + ddddddddddddddddd * eeeeeeeeeeeeeeeeee;
 end