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Fix higher order blackboxes not propagating usage metadata#3148

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3147-verilog-blackbox-for-iteratei-uses-wire-for-sequential-assignments
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Fix higher order blackboxes not propagating usage metadata#3148
rowanG077 wants to merge 1 commit intomasterfrom
3147-verilog-blackbox-for-iteratei-uses-wire-for-sequential-assignments

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@rowanG077 rowanG077 commented Feb 10, 2026

  • Write a changelog entry (see changelog/README.md)
  • Check copyright notices are up to date in edited files

@rowanG077 rowanG077 force-pushed the 3147-verilog-blackbox-for-iteratei-uses-wire-for-sequential-assignments branch from 755916f to c52cf26 Compare February 10, 2026 18:30
@rowanG077 rowanG077 changed the title FIXED: HO blackboxes not propagating usage metadata Fix HO blackboxes not propagating usage metadata Feb 10, 2026
@rowanG077 rowanG077 requested a review from lmbollen February 10, 2026 18:33
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rowanG077 commented Feb 10, 2026

Sad to say neither verilator or yosys catch this as a warning. And just text based checks really sucks because on my machine this text based check passes but I guess with different GHC/Clash combinations the exact ordering can be different.

@rowanG077 rowanG077 force-pushed the 3147-verilog-blackbox-for-iteratei-uses-wire-for-sequential-assignments branch 2 times, most recently from 10982ba to 53fee98 Compare February 11, 2026 10:19
@rowanG077 rowanG077 force-pushed the 3147-verilog-blackbox-for-iteratei-uses-wire-for-sequential-assignments branch from 53fee98 to 507b203 Compare February 11, 2026 13:59
@rowanG077 rowanG077 changed the title Fix HO blackboxes not propagating usage metadata Fix higher order blackboxes not propagating usage metadata Feb 11, 2026
@rowanG077 rowanG077 force-pushed the 3147-verilog-blackbox-for-iteratei-uses-wire-for-sequential-assignments branch from 507b203 to 661931c Compare February 11, 2026 14:01
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rowanG077 commented Feb 11, 2026

The given reproducer in the issue actually wasn't a reproducer, but with explicit clocks it does reproduce.

For the verification all sequential assignments to identifiers are gathered and it's checked the identifiers are declared as reg.

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I'm not 100% sure on the fix, but the tests look like they actually test something sensible to ✔️

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rowanG077 commented Feb 11, 2026

Let's wait for the grandmaster @christiaanb to see if he thinks this is the proper fix.

@rowanG077 rowanG077 requested review from christiaanb and removed request for lmbollen February 11, 2026 17:33
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Verilog blackbox for iterateI uses wire for sequential assignments

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