Skip to content
Syntactic checks

Verilog: introduce verilog_generate_declt #3801

Sign in to view logs

Verilog: introduce verilog_generate_declt

Verilog: introduce verilog_generate_declt #3801

Triggered via pull request January 9, 2026 18:20
@kroeningkroening
opened #1581
verilog_generate_decl
Status Failure
Total duration 1m 31s
Artifacts –

syntax-checks.yaml

on: pull_request
check-clang-format
1m 27s
check-clang-format
Fit to window
Zoom out
Zoom in

Annotations

1 error
check-clang-format
Process completed with exit code 1.