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Pull requests: diffblue/hw-cbmc

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Pull requests list

Verilog: support +define+ command line option
#2076 opened Aug 9, 2026 by kroening Collaborator Loading…
Verilog: add -y library directory option
#2075 opened Aug 9, 2026 by kroening Collaborator Loading…
Verilog: add +incdir+ command-line option
#2074 opened Aug 9, 2026 by kroening Collaborator Loading…
CI: publish benchmark reports to GitHub Pages
#2073 opened Aug 9, 2026 by kroening Collaborator Loading…
New IC3: extract blocking phase
#2072 opened Aug 9, 2026 by kroening Collaborator • Draft
New IC3: factor solver initialization
#2071 opened Aug 9, 2026 by kroening Collaborator • Draft
New IC3: extract property driver helpers
#2070 opened Aug 9, 2026 by kroening Collaborator • Draft
Verilog: support package export declarations
#2069 opened Aug 9, 2026 by kroening Collaborator • Draft
LogikBench: honor benchmark dependency filesets
#2068 opened Aug 9, 2026 by kroening Collaborator Loading…
Verilog: preserve genvars while elaborating module instances
#2067 opened Aug 9, 2026 by kroening Collaborator • Draft
New IC3: compare SAT backends on HWMCC17
#2066 opened Aug 9, 2026 by kroening Collaborator • Draft
Verilog: end labels after endfunction/endtask Verilog
#2065 opened Aug 9, 2026 by kroening Collaborator Loading…
Do not review
#2064 opened Aug 9, 2026 by kroening Collaborator • Draft
extract verilog_set_genvarst::build_map() cleanup Verilog
#2063 opened Aug 5, 2026 by kroening Collaborator Loading…
1
KNOWNBUG test for genvar as parameter argument Tests Verilog
#2062 opened Aug 4, 2026 by kroening Collaborator Loading…
1
Verilog: narrowing a wide output port to a one-bit net Verilog
#2061 opened Aug 4, 2026 by kroening Collaborator Loading…
Print version and architecture banner
#2060 opened Aug 4, 2026 by kroening Collaborator Loading…
Verilog: accept struct/array/union as constant expressions Verilog
#2059 opened Aug 1, 2026 by kroening Collaborator Loading…
KNOWNBUG test for struct-typed parameters Tests Verilog
#2057 opened Jul 24, 2026 by kroening Collaborator Loading…
1
Verilog preprocessor: replace, not append, on macro redefinition Verilog
#2056 opened Jul 24, 2026 by kroening Collaborator Loading…
Verilog preprocessor: track bracket nesting when splitting macro arguments Verilog
#2055 opened Jul 24, 2026 by kroening Collaborator Loading…
bump CBMC dependency dependencies Pull requests that update a dependency file
#2054 opened Jul 23, 2026 by kroening Collaborator • Draft
Verilog: fold Verilog-specific constructs when propagating constants in synthesis Verilog
#2053 opened Jul 23, 2026 by kroening Collaborator • Draft
Verilog: fix three type-checker gaps from LogikBench triage Verilog
#2052 opened Jul 23, 2026 by kroening Collaborator • Draft
Verilog: unpacked array parameter dimensions Verilog
#2051 opened Jul 23, 2026 by kroening Collaborator Loading…
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