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lines changed Original file line number Diff line number Diff line change 9
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* SystemVerilog: within
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* SystemVerilog: bugfix for |-> and |=>
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* SystemVerilog: bugfix for SVA sequence and
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+ * SystemVerilog: strong/weak sequence semantics
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* Verilog: 'dx, 'dz
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* SMV: LTL V operator, xnor operator
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* SMV: word types and operators
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- KNOWNBUG
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+ CORE
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cover_sequence2.sv
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- --bound 2
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- ^\[main\.p0\] cover \(main\.x == 2 ##1 main\.x == 3 ##1 main\.x == 100\): PROVED$
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- ^\[main\.p1\] cover \(main\.x == 98 ##1 main\.x == 99 ##1 main\.x == 100\): REFUTED up to bound 2$
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+ --bound 5
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+ ^\[main\.p0\] cover \(main\.x == 2 ##1 main\.x == 3 ##1 main\.x == 100\): REFUTED up to bound 5$
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+ ^\[main\.p1\] cover \(main\.x == 98 ##1 main\.x == 99 ##1 main\.x == 100\): REFUTED up to bound 5$
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+ ^\[main\.p2\] cover \(main\.x == 3 ##1 main\.x == 4 ##1 main\.x == 5\): PROVED$
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+ ^\[main\.p3\] cover \(main\.x == 4 ##1 main\.x == 5 ##1 main\.x == 6\): REFUTED up to bound 5$
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^EXIT=10$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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- Cover property p0 cannot ever hold, but is shown proven when using a small bound.
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module main (input clk);
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// count up
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- reg [ 7 : 0 ] x = 0 ;
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+ int x = 0 ;
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- always @ (posedge clk)
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+ always_ff @ (posedge clk)
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x++ ;
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// expected to fail
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p0: cover property (x== 2 ## 1 x== 3 ## 1 x== 100 );
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- // expected to fail until bound reaches 100
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+ // expected to fail until x reaches 100
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p1: cover property (x== 98 ## 1 x== 99 ## 1 x== 100 );
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+ // expected to pass once x reaches 5
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+ p2: cover property (x== 3 ## 1 x== 4 ## 1 x== 5 );
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+
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+ // expected to pass once x reaches 6
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+ p3: cover property (x== 4 ## 1 x== 5 ## 1 x== 6 );
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+
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endmodule
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+ CORE
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+ cover_sequence3.sv
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+ --bound 3
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+ ^\[main\.p0\] cover \(1 \[\*10\]\): REFUTED up to bound 3$
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+ ^\[main\.p1\] cover \(1 \[\*4:10\]\): PROVED$
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+ ^\[main\.p2\] cover \(1 \[\*5:10\]\): REFUTED up to bound 3$
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+ ^EXIT=10$
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+ ^SIGNAL=0$
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+ --
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+ ^warning: ignoring
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+ --
Original file line number Diff line number Diff line change
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+ module main (input clk);
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+
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+ // count up
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+ int x = 0 ;
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+
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+ always_ff @ (posedge clk)
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+ x++ ;
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+
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+ // passes with bound >=9
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+ p0: cover property (1 [* 10 ]);
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+
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+ // passes with bound >=3
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+ p1: cover property (1 [* 4 : 10 ]);
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+
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+ // passes with bound >=4
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+ p2: cover property (1 [* 5 : 10 ]);
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+
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+ endmodule
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+ KNOWNBUG
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+ cover_sequence4.sv
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+ --bound 3
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+ ^\[main\.p0\] cover \(1 \[=10\]\): REFUTED up to bound 3$
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+ ^\[main\.p1\] cover \(1 \[=4:10\]\): PROVED$
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+ ^\[main\.p2\] cover \(1 \[=5:10\]\): REFUTED up to bound 3$
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+ ^EXIT=10$
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+ ^SIGNAL=0$
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+ --
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+ ^warning: ignoring
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+ --
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+ Implementation of [=x:y] is missing.
Original file line number Diff line number Diff line change
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+ module main (input clk);
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+
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+ // count up
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+ int x = 0 ;
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+
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+ always_ff @ (posedge clk)
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+ x++ ;
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+
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+ // passes with bound >=9
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+ p0: cover property (1 [= 10 ]);
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+
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+ // passes with bound >=3
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+ p1: cover property (1 [= 4 : 10 ]);
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+
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+ // passes with bound >=4
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+ p2: cover property (1 [= 5 : 10 ]);
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+
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+ endmodule
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- KNOWNBUG
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+ CORE
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sequence2.sv
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- --bound 10 --numbered-trace
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- ^\[main\.p0] ##\[0:\$\] main\.x == 10: PROVED up to bound 10$
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- ^\[main\.p1] ##\[0:\$\] main\.x == 10: REFUTED$
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+ --bound 10
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+ ^\[main\.p0] weak\( ##\[0:\$\] main\.x == 10\) : PROVED up to bound 10$
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+ ^\[main\.p1] strong\( ##\[0:\$\] main\.x == 10\) : REFUTED$
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^EXIT=10$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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- strong(...) is missing.
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- KNOWNBUG
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+ CORE
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sequence3.sv
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--bound 20 --numbered-trace
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- ^\[main\.p0\] ##\[\*\] main\.x == 6: REFUTED$
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- ^\[main\.p1\] ##\[\*\] main\.x == 5: PROVED up to bound 20$
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- ^\[main\.p2\] ##\[\+\] main\.x == 0: REFUTED$
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- ^\[main\.p3\] ##\[\+\] main\.x == 5: PROVED up to bound 20$
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+ ^\[main\.p0\] strong\( ##\[\*\] main\.x == 6\) : REFUTED$
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+ ^\[main\.p1\] strong\( ##\[\*\] main\.x == 5\) : PROVED up to bound 20$
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+ ^\[main\.p2\] strong\( ##\[\+\] main\.x == 0\) : REFUTED$
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+ ^\[main\.p3\] strong\( ##\[\+\] main\.x == 5\) : PROVED up to bound 20$
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^EXIT=10$
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^SIGNAL=0$
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--
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^warning: ignoring
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--
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- strong(...) is missing
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CORE
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strong1.sv
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- --bound 20
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- ^\[main\.p0\] strong\(##\[0:9\] main\.x == 100 \): REFUTED$
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+ --bound 4
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+ ^\[main\.p0\] strong\(##\[0:9\] main\.x == 5 \): REFUTED$
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^EXIT=10$
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^SIGNAL=0$
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