Merge pull request #750 from diffblue/implicit-nets-type

Verilog: set type of implicit nets

Author: kroening

regression/verilog/nets/implicit1.desc

@@ -1,6 +1,6 @@
 CORE
 implicit1.sv
---bound 0
+--bound 0 --warn-implicit-nets
 ^file .* line 4: implicit wire main\.O$
 ^file .* line 4: implicit wire main\.A$
 ^file .* line 4: implicit wire main\.B$

regression/verilog/nets/implicit2.desc

@@ -1,9 +1,8 @@
-KNOWNBUG
+CORE
 implicit2.sv
---bound 0
+--bound 0 --warn-implicit-nets
 ^EXIT=0$
 ^SIGNAL=0$
 --
 ^warning: ignoring
 --
-The width of the implicit net is set incorrectly.

regression/verilog/nets/implicit3.desc

@@ -1,6 +1,6 @@
 CORE
 implicit3.sv
---bound 0
+--bound 0 --warn-implicit-nets
 ^file .* line 6: implicit wire main\.O$
 ^EXIT=0$
 ^SIGNAL=0$

regression/verilog/nets/implicit4.desc

@@ -1,9 +1,8 @@
-KNOWNBUG
+CORE
 implicit4.sv
---bound 0
+--bound 0 --warn-implicit-nets
 ^EXIT=0$
 ^SIGNAL=0$
 --
 ^warning: ignoring
 --
-The width of the implicit net is set incorrectly.

regression/verilog/nets/implicit5.desc

@@ -1,9 +1,9 @@
-KNOWNBUG
+CORE
 implicit5.sv
---bound 0
-^EXIT=0$
+--bound 0 --warn-implicit-nets
+^file .* line 4: unknown identifier A$
+^EXIT=2$
 ^SIGNAL=0$
 --
 ^warning: ignoring
 --
-This case should be errored.

regression/verilog/nets/implicit6.desc

@@ -0,0 +1,8 @@
+CORE
+implicit6.sv
+--bound 0 --warn-implicit-nets
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--

regression/verilog/nets/implicit6.sv

@@ -0,0 +1,10 @@
+module main;
+
+  parameter P = 2;
+
+  // implicit nets are allowed in the port connection list of a module
+  and [P:0] (O, A, B);
+
+  assert final ($bits(O) == P+1);
+
+endmodule

regression/verilog/nets/implicit7.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+implicit7.sv
+--bound 0 --warn-implicit-nets
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+The implicit net is not known yet when evaluating parameters.

regression/verilog/nets/implicit7.sv

@@ -0,0 +1,16 @@
+module main;
+
+  parameter P = 10;
+
+  // implicit nets are allowed in the port connection list of a module
+  sub #(P) my_sub(x);
+
+  // The type of the implict net could be used to define another parameter
+  parameter Q = $bits(x);
+
+  assert final (Q == P + 1);
+
+endmodule
+
+module sub #(parameter P = 1)(input [P:0] some_input);
+endmodule

src/ebmc/ebmc_parse_options.h

@@ -47,7 +47,8 @@ class ebmc_parse_optionst:public parse_options_baset
         "(random-traces)(trace-steps):(random-seed):(traces):"
         "(random-trace)(random-waveform)"
         "(liveness-to-safety)"
-        "I:D:(preprocess)(systemverilog)(vl2smv-extensions)",
+        "I:D:(preprocess)(systemverilog)(vl2smv-extensions)"
+        "(warn-implicit-nets)",
         argc,
         argv,
         std::string("EBMC ") + EBMC_VERSION),