Merge pull request #372 from diffblue/vector_types1

Verilog: add a test for the vector types

Author: tautschnig

regression/verilog/data-types/vector_types1.desc

@@ -0,0 +1,6 @@
+CORE
+vector_types1.sv
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--

regression/verilog/data-types/vector_types1.sv

@@ -0,0 +1,24 @@
+module main;
+
+  wire [7:0] implicit;
+  wire bit [7:0] some_bits;
+  wire logic [7:0] some_logic;
+  wire unsigned [7:0] implicit_unsigned;
+  wire bit unsigned [7:0] some_bits_unsigned;
+  wire logic unsigned [7:0] some_logic_unsigned;
+  wire signed [7:0] implicit_signed;
+  wire bit signed [7:0] some_bits_signed;
+  wire logic signed [7:0] some_logic_signed;
+
+  // expected to pass
+  p0: assert property ($bits(implicit) == 8);
+  p1: assert property ($bits(some_bits) == 8);
+  p2: assert property ($bits(some_logic) == 8);
+  p3: assert property ($bits(implicit_unsigned) == 8);
+  p4: assert property ($bits(some_bits_unsigned) == 8);
+  p5: assert property ($bits(some_logic_unsigned) == 8);
+  p6: assert property ($bits(implicit_signed) == 8);
+  p7: assert property ($bits(some_bits_signed) == 8);
+  p8: assert property ($bits(some_logic_signed) == 8);
+
+endmodule