Merge pull request #1108 from diffblue/interconnect1

KNOWNBUG test for `interconnect`

Author: tautschnig

regression/verilog/modules/interconnect1.desc

@@ -0,0 +1,8 @@
+KNOWNBUG
+interconnect1.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+--
+interconnect is not implemented.

regression/verilog/modules/interconnect1.sv

@@ -0,0 +1,11 @@
+module top;
+  interconnect bus;
+  mod1 m1(bus);
+  mod2 m2(bus);
+endmodule
+
+module mod1(input in);
+endmodule
+
+module mod2(output out);
+endmodule