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Merge pull request #364 from diffblue/verilog-fix-symbols
Verilog: clean up base_name vs identifier in declarators
2 parents 2ba20d2 + cbae8e1 commit 9b1c261

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4 files changed

+24
-28
lines changed

4 files changed

+24
-28
lines changed
Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,7 @@
1-
KNOWNBUG
1+
CORE
22
typedef_name_collision1.sv
33

4+
^file .* line 6: definition of symbol `some_identifier' conflicts with earlier definition at line 3$
45
^EXIT=2$
56
^SIGNAL=0$
67
--
7-
--
8-
The name collision should be errored.

src/verilog/parser.y

Lines changed: 8 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -122,7 +122,9 @@ Function: new_symbol
122122
inline static void new_symbol(YYSTYPE &dest, YYSTYPE &src)
123123
{
124124
init(dest, ID_symbol);
125-
addswap(dest, ID_identifier, src);
125+
const auto base_name = stack_expr(src).id();
126+
stack_expr(dest).set(ID_identifier, base_name);
127+
stack_expr(dest).set(ID_base_name, base_name);
126128
}
127129

128130
/*******************************************************************\
@@ -1538,7 +1540,9 @@ list_of_param_assignments:
15381540

15391541
param_assignment: param_identifier '=' const_expression
15401542
{ init($$, ID_parameter);
1541-
addswap($$, ID_identifier, $1);
1543+
auto base_name = stack_expr($1).id();
1544+
stack_expr($$).set(ID_identifier, base_name);
1545+
stack_expr($$).set(ID_base_name, base_name);
15421546
addswap($$, ID_value, $3); }
15431547
;
15441548

@@ -2498,9 +2502,7 @@ statement_item:
24982502
;
24992503

25002504
system_task_name: TOK_SYSIDENT
2501-
{ init($$, ID_symbol);
2502-
stack_expr($$).set(ID_identifier, stack_expr($1).id());
2503-
}
2505+
{ new_symbol($$, $1); }
25042506
;
25052507

25062508
// System Verilog standard 1800-2017
@@ -3182,7 +3184,7 @@ type_identifier: TOK_TYPE_IDENTIFIER
31823184
{
31833185
init($$, ID_typedef_type);
31843186
auto base_name = stack_expr($1).id();
3185-
stack_expr($$).set(ID_C_base_name, base_name);
3187+
stack_expr($$).set(ID_base_name, base_name);
31863188
stack_expr($$).set(ID_identifier, PARSER.current_scope->prefix+id2string(base_name));
31873189
}
31883190
;

src/verilog/verilog_expr.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -424,7 +424,7 @@ class verilog_parameter_declt : public verilog_module_itemt
424424

425425
const irep_idt &base_name() const
426426
{
427-
return get(ID_identifier);
427+
return get(ID_base_name);
428428
}
429429

430430
const exprt &value() const

src/verilog/verilog_interfaces.cpp

Lines changed: 13 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -65,53 +65,48 @@ void verilog_typecheckt::check_module_ports(
6565

6666
const auto &declarator = decl.declarators().front();
6767

68-
const irep_idt &name = declarator.identifier();
68+
const irep_idt &base_name = declarator.base_name();
6969

70-
if(name.empty())
70+
if(base_name.empty())
7171
{
7272
throw errort().with_location(decl.source_location())
7373
<< "empty port name (module " << module_symbol.base_name << ')';
7474
}
7575

76-
if(port_names.find(name)!=
77-
port_names.end())
76+
if(port_names.find(base_name) != port_names.end())
7877
{
79-
error().source_location = declarator.source_location();
80-
error() << "duplicate port name: `" << name << '\'' << eom;
81-
throw 0;
78+
throw errort().with_location(declarator.source_location())
79+
<< "duplicate port name: `" << base_name << '\'';
8280
}
8381

84-
irep_idt identifier=
85-
id2string(module_identifier)+"."+id2string(name);
86-
82+
irep_idt identifier = hierarchical_identifier(base_name);
83+
8784
const symbolt *port_symbol=0;
8885

8986
// find the symbol
9087

9188
if(ns.lookup(identifier, port_symbol))
9289
{
9390
throw errort().with_location(declarator.source_location())
94-
<< "port `" << name << "' not declared";
91+
<< "port `" << base_name << "' not declared";
9592
}
9693

9794
if(!port_symbol->is_input && !port_symbol->is_output)
9895
{
99-
error().source_location = declarator.source_location();
100-
error() << "port `" << name
101-
<< "' not declared as input or output" << eom;
102-
throw 0;
96+
throw errort().with_location(declarator.source_location())
97+
<< "port `" << base_name << "' not declared as input or output";
10398
}
10499

105-
ports[nr].set("#name", name);
100+
ports[nr].set("#name", base_name);
106101
ports[nr].id(ID_symbol);
107102
ports[nr].set(ID_identifier, identifier);
108103
ports[nr].set(ID_C_source_location, declarator.source_location());
109104
ports[nr].set(ID_type, port_symbol->type);
110105
ports[nr].set(ID_input, port_symbol->is_input);
111106
ports[nr].set(ID_output, port_symbol->is_output);
112107

113-
port_names[name]=nr;
114-
108+
port_names[base_name] = nr;
109+
115110
nr++;
116111
}
117112

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