Verilog: KNOWNBUG test for enum base type that depends on parameter

Author: kroening

regression/verilog/enums/enum_base_type2.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+enum_base_type2.sv
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+^\[.*\] always 8 == 8: PROVED up to bound 0$
+--
+--
+The base type of an enum may depend on an elaboration-time constant.

regression/verilog/enums/enum_base_type2.sv

@@ -0,0 +1,11 @@
+module main;
+
+  // The base type of an enum may depend on an elaboration-time constant.
+  typedef enum bit [p:1] { A } enum_t;
+
+  parameter p = 8;
+
+  // expected to pass
+  p1: assert property ($bits(A) == p);
+
+endmodule