Correctly check memory alignment based on size of operand

[mininny]

Description

The RISC-V specifications indicate the following in section "14.2. "Zalrsc" Extension for Load-Reserved/Store-Conditional Instructions".

For LR and SC, the Zalrsc extension requires that the address held in rs1 be naturally aligned to the
size of the operand (i.e., eight-byte aligned for doublewords and four-byte aligned for words). If the
address is not naturally aligned, an address-misaligned exception or an access-fault exception will be
generated.

However, the current implementation only checks that the address is aligned on 4 bytes. This check is not accurate for LR.D and SC.D instructions which use 8-byte size.

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This PR ensures that mod(addr, size) == 0 instead of the current logical and check.

[codecov-commenter]

Codecov Report

Attention: Patch coverage is 0% with 2 lines in your changes missing coverage. Please review.

Project coverage is 61.89%. Comparing base (8ff9318) to head (b7dc265).

Files with missing lines	Patch %	Lines
rvgo/fast/vm.go	0.00%	0 Missing and 1 partial ⚠️
rvgo/slow/vm.go	0.00%	0 Missing and 1 partial ⚠️

Additional details and impacted files

@@           Coverage Diff           @@
##           master     #106   +/-   ##
=======================================
  Coverage   61.89%   61.89%           
=======================================
  Files          27       27           
  Lines        4091     4091           
=======================================
  Hits         2532     2532           
  Misses       1427     1427           
  Partials      132      132           

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[BlocksOnAChain]

@mininny we can merge now since it was approved by Refcell and approved by the auditors.