These projects are part of the CSC-137 class at California State University, Sacramento
The purpose of these projects is to apply hands-on knowledge about circuit, gates logic and verilog. Each project is built on top of each other. Project 3 is a 7 bit sequential 2's complement multiplier that ultilize the 2-bit CLA adder in project 1.
Verilog
While these are my projects/assignments in CSC-137, it is for personal use and it is not advisable to reuse or copy these projects if you are current students in CSC-137, I take no credit if you're caught for cheating/plagiarism