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Merge pull request #55 from asanza/fix_priority_execution
Fix execution priority.
2 parents 2a2c510 + 0bdfd4e commit c4d2b04

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zmu_cortex_m/src/core/exception.rs

Lines changed: 37 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -355,11 +355,29 @@ impl ExceptionHandling for Processor {
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let mut highestpri: i16 = 256;
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let mut boostedpri: i16 = 256;
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let subgroupshift = self.aircr.get_bits(8..11);
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let groupvalue = 2 << subgroupshift;
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let mut groupvalue = 2 << subgroupshift;
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for (_, exp) in self.exceptions.iter().filter(|&(_, e)| e.active) {
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if exp.priority < highestpri {
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highestpri = exp.priority;
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/*
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ARMV7-M Arch Reference Manual. Version E. Page B1-527
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Priority Grouping. The group priority for Reset, NMI
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and HardFault are -3, -2 and -1 respectively, regardless
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of the value of PRIGROUP. Note that we dont check reset because
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after setting the reset pending flag, the simulator resets the
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processor.
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*/
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if exp.exception_number == Exception::NMI.into() {
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groupvalue = -2;
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}
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if exp.exception_number == Exception::HardFault.into() {
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groupvalue = -1;
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}
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let subgroupvalue = highestpri % groupvalue;
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highestpri -= subgroupvalue;
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}
@@ -645,6 +663,24 @@ mod tests {
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assert!(core.exception_active(Exception::BusFault));
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}
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#[test]
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fn test_get_execution_priority() {
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let mut p = Processor::new();
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p.reset().unwrap();
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p.msp = 0x2000_0400;
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p.set_exception_pending(Exception::HardFault);
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p.check_exceptions();
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assert_eq!(p.get_execution_priority(), -1);
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p.reset().unwrap();
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p.msp = 0x2000_0400;
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p.set_exception_pending(Exception::NMI);
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p.check_exceptions();
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assert_eq!(p.get_execution_priority(), -2);
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}
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#[test]
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fn test_exception_priority() {
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// Arrange

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