Changes to try to fix #929

jotego · Jan 23, 2025 · d755397 · d755397
1 parent 5675f4c
commit d755397
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Showing 8 changed files with 31 additions and 12 deletions.
diff --git a/cores/fround/hdl/jt00778x.v b/cores/fround/hdl/jt00778x.v
@@ -60,6 +60,7 @@ module jt00778x#(parameter CW=17,PW=10)(    // sprite logic
     input             lvbl,
     input    [PW-1:0] obj_dx, obj_dy,
     input             gvflip,
+    output reg        objbufinit,
 
     // draw module
     output   [CW-1:0] code,
@@ -77,7 +78,8 @@ module jt00778x#(parameter CW=17,PW=10)(    // sprite logic
 wire   [15:0] scan_dout;
 wire   [13:1] dma_addr, copy_addr;
 wire   [10:1] scan_addr;
-wire          objbufinit, copy_bsy;
+wire          copy_bsy;
+reg           hs_l, copyinit;
 
 localparam NOLUTFB=`ifdef NOLUTFB 1 `else 0 `endif;
 
@@ -91,8 +93,14 @@ assign oram_addr = copy_bsy ? copy_addr :
 // skip LUT
 assign oram_addr = {3'b110, scan_addr};
 `endif
-// original equation from schematics, it is the same as the start of vblank
-assign objbufinit = ~|{ (~&vdump[7:5] | ~&{vdump[4],~vdump[3]}), vdump[2:1] };
+always @(posedge clk) begin
+    hs_l <= hs;
+    if( hs && !hs_l) begin
+        // original equation from schematics, it is the same as the start of vblank
+        objbufinit <= ~|{ (~&vdump[7:5] | ~&{vdump[4],~vdump[3]}), vdump[2:1] };
+        copyinit   <= vdump == 9'h10B;
+    end
+end
 
 jt00778x_dma #(.PW(PW)) u_dma(
     .rst        ( rst           ),
@@ -124,7 +132,7 @@ jt00778x_copy_lut u_copy_lut(
     .rst        ( rst           ),
     .clk        ( clk           ),
     .pxl_cen    ( pxl_cen       ),
-    .objbufinit ( objbufinit    ),
+    .objbufinit ( copyinit      ),
     .dma_on     ( dma_on        ),
     .dma_bsy    ( copy_bsy      ),
 

diff --git a/cores/fround/hdl/jt00778x_copy_lut.v b/cores/fround/hdl/jt00778x_copy_lut.v
@@ -46,9 +46,9 @@ always @(posedge clk) begin
         dma_cen <= ~dma_cen; // not really a cen, must be combined with pxl_cen
         obi_l   <= objbufinit;
         if( objbufinit && !obi_l ) begin
-            if(dma_on) begin
+            // if(dma_on) begin
                 dma_bsy <= 1;
-            end
+            // end
             lo_addr <= 0;
         end
         if( dma_bsy ) begin

diff --git a/cores/fround/hdl/jt00778x_dma.v b/cores/fround/hdl/jt00778x_dma.v
@@ -75,7 +75,7 @@ always @(posedge clk) begin
         end else if( dma_bsy ) begin
             if( dma_clr && dma_cen ) begin
                 { dma_clr, cpw_addr } <= nx_cpwa;
-                oram_we <= obj_en & nx_cpwa[11];
+                oram_we <= (obj_en | objbufinit) & nx_cpwa[11];
             end else if( !dma_clr ) begin // direct copy
                 if( !dma_cen ) begin
                     case( cpr_addr[3:1] )

diff --git a/cores/twin16/hdl/jttwin16_game.v b/cores/twin16/hdl/jttwin16_game.v
@@ -35,6 +35,7 @@ wire [ 1:0] vam_we, vbm_we, om_we, stile_we16,
 reg  [ 7:0] debug_mux, ioctl_mux;
 wire        oram_wex;
 wire [ 2:0] prio;
+wire objbufinit;
 
 assign main_addr  = m_addr[17:1];
 assign mram_addr  = m_addr[13:1];
@@ -107,6 +108,7 @@ jttwin16_share u_share(
     .cen            ( cen_1m5       ),
     .tim1           ( tim1          ),  // main CPU has access to video
     .tim2           ( tim2          ),  // sub CPU does
+    .dma_bsy        ( objbufinit    ),
     // main CPU
     .m_addr         ( m_addr[13:1]  ),
     .m_dout         ( m_dout        ),
@@ -270,6 +272,7 @@ jttwin16_video u_video (
 
     .dma_on         ( dma_on        ),
     .dma_bsy        ( dma_bsy       ),
+    .objbufinit     ( objbufinit    ),
 
     .lhbl           ( LHBL          ),
     .lvbl           ( LVBL          ),

diff --git a/cores/twin16/hdl/jttwin16_main.v b/cores/twin16/hdl/jttwin16_main.v
@@ -94,7 +94,7 @@ wire [15:0] vdout;
 reg  [ 7:0] cab_dout;
 reg  [ 4:0] nvram_ahi;
 reg         LVBLl;
-wire        bus_cs, bus_busy, BUSn, ab_sel;
+wire        bus_cs, bus_busy, BUSn, ab_sel, bus_legit;
 
 `ifdef SIMULATION
 wire [23:0] A_full = {A,1'b0};
@@ -103,8 +103,8 @@ wire [23:0] A_full = {A,1'b0};
 assign main_addr  = A[19:1];
 assign nvram_addr = {nvram_ahi,A[9:1]};
 assign ram_dsn    = {UDSn, LDSn};
-assign bus_cs     = rom_cs | ram_cs;
-assign bus_busy   = (rom_cs  & ~rom_ok) | (ram_cs  & ~ram_ok);
+assign bus_cs     = rom_cs | ram_cs | oram_cs;
+assign bus_busy   = (rom_cs  & ~rom_ok) | (ram_cs  & ~ram_ok) | (oram_cs & dma_bsy);
 assign BUSn       = ASn | (LDSn & UDSn);
 assign cpu_we     = ~RnW;
 assign ram_we     = ~RnW;
@@ -117,6 +117,7 @@ assign va_we      = dws & {2{vram_cs & ~A[13]}};
 assign vb_we      = dws & {2{vram_cs &  A[13]}};
 assign fx_we      = dws & {2{fix_cs}};
 assign oram_we    = dws & {2{oeff_cs}};
+assign bus_legit  = oram_cs;
 
 always @* begin
     case( debug_bus[3:0] )
@@ -280,7 +281,7 @@ jtframe_68kdtack_cen #(.W(5),.RECOVERY(1)) u_dtack(
     .cpu_cenb   ( cpu_cenb  ),
     .bus_cs     ( bus_cs    ),
     .bus_busy   ( bus_busy  ),
-    .bus_legit  ( 1'b0      ),
+    .bus_legit  ( bus_legit ),
     .ASn        ( ASn       ),
     .DSn        ({UDSn,LDSn}),
     .num        ( 4'd3      ),  // numerator

diff --git a/cores/twin16/hdl/jttwin16_obj.v b/cores/twin16/hdl/jttwin16_obj.v
@@ -40,6 +40,7 @@ module jttwin16_obj(
 
     input             dma_on,
     output            dma_bsy,
+    output            objbufinit,
 
     // ROM addressing
     output reg [21:2] rom_addr, // code + 1 bit. VH mostly embedded in core
@@ -84,6 +85,7 @@ jt00778x #(.CW(CW),.PW(16)) u_scan(    // sprite logic
     .obj_dx         ( obj_dx        ),
     .obj_dy         ( obj_dy        ),
     .gvflip         ( vflip         ),
+    .objbufinit     ( objbufinit    ),
 
     // ROM addressing
     .code           ( code          ),

diff --git a/cores/twin16/hdl/jttwin16_share.v b/cores/twin16/hdl/jttwin16_share.v
@@ -25,6 +25,8 @@ module jttwin16_share(
     output reg           tim1=0,// main CPU has access to video
     output reg           tim2=0,// sub CPU does
 
+    input                dma_bsy,
+
     input         [15:0] m_dout, s_dout,
     output        [15:0] v_din,
     input         [13:1] m_addr, s_addr,
@@ -54,7 +56,8 @@ always @(posedge |os_we) osa_l <= s_addr;
 `endif
 
 assign v_din     = tim1 ? m_dout : s_dout;
-assign oram_we   = tim1 ? om_we  : os_we;
+// assign oram_we   = tim1 ? om_we  : os_we;
+assign oram_we   = (tim1 ? om_we : os_we ) & {2{~dma_bsy}};
 assign va_we     = tim1 ? vam_we : vas_we;
 assign vb_we     = tim1 ? vbm_we : vbs_we;
 assign osha_addr = tim1 ? m_addr : s_addr;

diff --git a/cores/twin16/hdl/jttwin16_video.v b/cores/twin16/hdl/jttwin16_video.v
@@ -35,6 +35,7 @@ module jttwin16_video(
 
     input             dma_on,
     output            dma_bsy,
+    output            objbufinit,
 
     input             hflip,
     input             vflip,
@@ -286,6 +287,7 @@ jttwin16_obj u_obj(
 
     .dma_on     ( dma_on    ),
     .dma_bsy    ( dma_bsy   ),
+    .objbufinit ( objbufinit),
 
     .rom_addr   ( lyro_addr ),
     .rom_data   ( osorted   ),