perf(deepseek-v4): accelerate indexer Q and packed FP8 quantization

[dongjiyingdjy]

Summary

• Add an SM100-specialized DeepSeek-V4 indexer-Q path using adapted TensorRT-LLM MLA RoPE and fusedCat FP4 CUDA kernels behind the tokenspeed-kernel boundary.
• Add an SM100 packed-UE8M0 FP8 online quantizer for DeepGEMM activation quantization.
• Remove DeepSeek-V4 prefill host synchronizations by planning metadata from pinned CPU length mirrors, reusing persistent buffers, and writing indexer top-k results directly to their destination.
• Rebase the full stack onto current main and preserve the algorithm-specific CUDA Graph padding behavior from fix(perf): fix qwen3.5 tp8 agentic ci perf regression #594: MTP attention rows use request slot 0, DFLASH rows use the reserved sentinel, and state writes continue to use the sentinel sink.
• Fix the rebased indexer-Q path to import Hadamard transforms through tokenspeed_kernel.ops.transform. The old thirdparty.fast_hadamard_transform module was removed on main; its guarded import silently disabled the optimized Q-preparation path.

The two CUDA adapters are derived from TensorRT-LLM commit 1a4fc3e05cea6e2843db8ba7a14e0c3a1a2a7018 and retain NVIDIA's Apache-2.0 attribution.

Performance

Indexer Q

On B200, the eager Q-preparation microbenchmark improves from 1.57x at 128 tokens to 13.28x at 4,632 tokens. Small eager shapes remain on Triton because the multi-launch CUDA chain is slower there.

One fresh-server p1/p2/p4/p8 matched run improved TPS/GPU by 13.43%, 16.29%, 18.86%, and 20.73%, respectively. These endpoint numbers remain provisional because they have one paired repeat and predate the exact current stacked HEAD.

Packed FP8 quantization

With production PDL=False, the B200 quantization microbenchmark improves:

• Prefill chain: 24.0257 ms -> 4.6818 ms per rank (5.13x).
• Decode CUDA Graph replay: 0.6546 ms -> 0.3965 ms per step (1.65x).

Two matched V4-Pro p1/p2/p4/p8 endpoint pairs completed all requests. Their aggregate median improvements were:

• TPS/GPU: +3.83%, +3.73%, +4.14%, and +4.27%.
• TPOT: +2.88%, +3.19%, +4.00%, and +4.59%.

The aggregate medians are +3.98% TPS/GPU and +3.60% TPOT. The strict overall performance result remains inconclusive because p8 TTFT changed sign across the two pairs and no third pair was run during exploratory validation.

Prefill host synchronization cleanup

The runtime derives prefill workspace and indexer metadata from CPU length mirrors, reuses persistent request/prefix buffers for state reset, removes dead indexer slot metadata, and writes top-k output directly into the destination buffer. CUDA Graph tail padding preserves both the speculative verify-width contract and reserved state-write sink rows.

Main-rebase compatibility fix

A matched TP8 p8 cold SWE-smith diagnostic used eight concurrent, byte-identical prompts with 530,171 total prompt tokens and 500 output tokens per request. Restoring the registered Hadamard path changed:

• Capture wall time: 53.801 s -> 39.067 s (-27.39%).
• Output throughput: 74.348 -> 102.389 tokens/s (+37.72%).
• Indexer-Q prefill GPU time: 92.166 -> 6.640 GPU-s (13.88x).

This profile contains complete prefill and decode, with 8/8 successful requests. It is diagnostic attribution, not a replacement for a full matched p1/p2/p4/p8 sweep.

Validation

Exact rebased HEAD: 63f0b66d4.

• pre-commit run --all-files: passed.
• Indexer-Q registration and public transform-boundary tests: 2 passed.
• Real-B200 indexer-Q fused-Triton parity and CUDA Graph replay tests: 3 passed.
• CUDA Graph padding and speculative sequence-length regression tests: 21 passed.
• V4-Flash GSM8K: 5-shot, 50 samples, concurrency 1, temperature 0; strict and flexible exact match both 0.94 (47/50), above the required 0.92 gate.
• All 50 GSM8K requests completed; post-evaluation readiness/health checks passed and the fatal-log scan was empty.
• The matched TP8 p8 SWE-smith Nsys rerun completed 8/8 requests and covered full prefill plus decode.

Risk and fallback

Both SM100 fast paths are optional optimizations.

The indexer path falls back to the existing fused Triton implementation for small batches and unsupported architectures, shapes, dtypes, layouts, or alignments. It applies RoPE to index_q in place; the production caller supplies a disposable projection output. TensorRT-LLM evaluation order may produce rare FP4 rounding-boundary differences, while reference tests and the V4-Flash gate pass.

The packed quantizer requires a contiguous, aligned CUDA BF16 matrix with K divisible by 128 and the packed-UE8M0 scale contract. Unsupported inputs or an unavailable extension use the existing quantization path. PDL remains disabled by default, and the adapter preserves TokenSpeed's existing tiny-scale floor.

The prefill cleanup relies on CPU length mirrors remaining consistent with dispatch. Its two pinned staging slots match the scheduler's current maximum overlap depth of one; a deeper pipeline must expand the ring to depth + 1.

Follow-up

Once equivalent APIs are exposed by tokenspeed_trtllm_kernel, replace both standalone vendored extensions--the indexer-Q kernels and packed FP8 quantizer--with imports from that package.