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[PowerPC] Fix assert exposed by PR 95931 in LowerBITCAST #108062

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Merged
merged 3 commits into from
Sep 10, 2024
Merged

[PowerPC] Fix assert exposed by PR 95931 in LowerBITCAST #108062

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759aeb6
[PowerPC] Fix assert exposed by PR 95931 in LowerBITCAST
Sep 10, 2024
5fc0f2c
Address review comments
Sep 10, 2024
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Address review
Sep 10, 2024
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9 changes: 5 additions & 4 deletions llvm/lib/Target/PowerPC/PPCISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -9470,12 +9470,13 @@ SDValue PPCTargetLowering::LowerBITCAST(SDValue Op, SelectionDAG &DAG) const {
SDLoc dl(Op);
SDValue Op0 = Op->getOperand(0);

if (!Subtarget.isPPC64() || (Op0.getOpcode() != ISD::BUILD_PAIR) ||
(Op.getValueType() != MVT::f128))
return SDValue();

SDValue Lo = Op0.getOperand(0);
SDValue Hi = Op0.getOperand(1);

if ((Op.getValueType() != MVT::f128) ||
(Op0.getOpcode() != ISD::BUILD_PAIR) || (Lo.getValueType() != MVT::i64) ||
(Hi.getValueType() != MVT::i64) || !Subtarget.isPPC64())
if ((Lo.getValueType() != MVT::i64) || (Hi.getValueType() != MVT::i64))
return SDValue();

if (!Subtarget.isLittleEndian())
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22 changes: 22 additions & 0 deletions llvm/test/CodeGen/PowerPC/f128-bitcast.ll
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Expand Up @@ -86,3 +86,25 @@ entry:
ret i64 %1
}

define <4 x i32> @truncBitcast(i512 %a) {
; CHECK-LABEL: truncBitcast:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mtvsrdd v2, r4, r3
; CHECK-NEXT: blr
;
; CHECK-BE-LABEL: truncBitcast:
; CHECK-BE: # %bb.0: # %entry
; CHECK-BE-NEXT: mtvsrdd v2, r9, r10
; CHECK-BE-NEXT: blr
;
; CHECK-P8-LABEL: truncBitcast:
; CHECK-P8: # %bb.0: # %entry
; CHECK-P8-NEXT: mtfprd f0, r3
; CHECK-P8-NEXT: mtfprd f1, r4
; CHECK-P8-NEXT: xxmrghd v2, vs1, vs0
; CHECK-P8-NEXT: blr
entry:
%0 = trunc i512 %a to i128
%1 = bitcast i128 %0 to <4 x i32>
ret <4 x i32> %1
}
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