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[RISCV] Add more patten for FMA instruction to eliminate the fneg #173808

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[RISCV] Add more patten for FMA instruction to eliminate the fneg #173808

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08190d6
init testcase
ChunyuLiao Dec 26, 2025
bd73cfe
[RISCV] Add more patten for FMA instruction to eliminate the fneg
ChunyuLiao Dec 26, 2025
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16 changes: 16 additions & 0 deletions llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1326,6 +1326,22 @@ foreach fvti = AllFloatVectors in {
// RISCVInsertReadWriteCSR
FRM_DYN,
fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fvti.Vector (any_fma (SplatFPOp (fneg fvti.ScalarRegClass:$rs1)),
fvti.RegClass:$rd, (fneg fvti.RegClass:$rs2))),
(!cast<Instruction>("PseudoVFNMADD_V" # fvti.ScalarSuffix # "_" # suffix)
fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fvti.Vector (any_fma (SplatFPOp (fneg fvti.ScalarRegClass:$rs1)),
fvti.RegClass:$rd, fvti.RegClass:$rs2)),
(!cast<Instruction>("PseudoVFNMSUB_V" # fvti.ScalarSuffix # "_" # suffix)
fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
}
}

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46 changes: 46 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/vsplats-zfa.ll
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Expand Up @@ -33,3 +33,49 @@ define <vscale x 8 x double> @vsplat_f64_neg1() {
; CHECK-NEXT: ret
ret <vscale x 8 x double> splat (double -1.0)
}

define <vscale x 4 x float> @vfnmsac(<vscale x 4 x float> %va, <vscale x 4 x float> %vb) {
; CHECK-LABEL: vfnmsac:
; CHECK: # %bb.0:
; CHECK-NEXT: fli.s fa5, 2.0
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vfnmsac.vf v8, fa5, v10
; CHECK-NEXT: ret
%vd = tail call <vscale x 4 x float> @llvm.fmuladd.nxv4f32(<vscale x 4 x float> %vb, <vscale x 4 x float> splat (float -2.000000e+00), <vscale x 4 x float> %va)
ret <vscale x 4 x float> %vd
}

define <vscale x 4 x float> @vfnmsub(<vscale x 4 x float> %va, <vscale x 4 x float> %vb) {
; CHECK-LABEL: vfnmsub:
; CHECK: # %bb.0:
; CHECK-NEXT: fli.s fa5, 2.0
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
; CHECK-NEXT: vfnmsub.vf v8, fa5, v10
; CHECK-NEXT: ret
%vd = tail call <vscale x 4 x float> @llvm.fmuladd.nxv4f32(<vscale x 4 x float> splat (float -2.000000e+00), <vscale x 4 x float> %va, <vscale x 4 x float> %vb)
ret <vscale x 4 x float> %vd
}

define <vscale x 8 x float> @vfnmacc(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: vfnmacc:
; CHECK: # %bb.0:
; CHECK-NEXT: fli.s fa5, 2.0
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vfnmacc.vf v8, fa5, v12
; CHECK-NEXT: ret
%neg = fneg <vscale x 8 x float> %va
%vd = call <vscale x 8 x float> @llvm.fma.v8f32(<vscale x 8 x float> %vb, <vscale x 8 x float> splat (float -2.000000e+00), <vscale x 8 x float> %neg)
ret <vscale x 8 x float> %vd
}

define <vscale x 8 x float> @vfnmadd(<vscale x 8 x float> %va, <vscale x 8 x float> %vb) {
; CHECK-LABEL: vfnmadd:
; CHECK: # %bb.0:
; CHECK-NEXT: fli.s fa5, 2.0
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
; CHECK-NEXT: vfnmadd.vf v8, fa5, v12
; CHECK-NEXT: ret
%neg = fneg <vscale x 8 x float> %vb
%vd = call <vscale x 8 x float> @llvm.fma.v8f32(<vscale x 8 x float> %va, <vscale x 8 x float> splat (float -2.000000e+00), <vscale x 8 x float> %neg)
ret <vscale x 8 x float> %vd
}