[RISCV] Remove codegen for vp_fp_to_{u,s}int, vp_{u,s}int_to_fp#190576
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[RISCV] Remove codegen for vp_fp_to_{u,s}int, vp_{u,s}int_to_fp#190576
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Part of the work to remove trivial VP intrinsics from the RISC-V backend, see https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999 This splits off 4 intrinsics from llvm#179622.
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@llvm/pr-subscribers-backend-risc-v Author: Luke Lau (lukel97) ChangesPart of the work to remove trivial VP intrinsics from the RISC-V backend, see https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999 This splits off 4 intrinsics from #179622. Patch is 256.25 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/190576.diff 19 Files Affected:
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d00b734f64509..a472dffd93f0d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -874,8 +874,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::VP_SHL, ISD::VP_REDUCE_ADD, ISD::VP_REDUCE_AND,
ISD::VP_REDUCE_OR, ISD::VP_REDUCE_XOR, ISD::VP_REDUCE_SMAX,
ISD::VP_REDUCE_SMIN, ISD::VP_REDUCE_UMAX, ISD::VP_REDUCE_UMIN,
- ISD::VP_MERGE, ISD::VP_SELECT, ISD::VP_FP_TO_SINT,
- ISD::VP_FP_TO_UINT, ISD::VP_SETCC, ISD::VP_SIGN_EXTEND,
+ ISD::VP_MERGE, ISD::VP_SELECT, ISD::VP_SETCC,
+ ISD::VP_SIGN_EXTEND,
ISD::VP_ZERO_EXTEND, ISD::VP_TRUNCATE, ISD::VP_SMIN,
ISD::VP_SMAX, ISD::VP_UMIN, ISD::VP_UMAX,
ISD::VP_ABS, ISD::EXPERIMENTAL_VP_REVERSE, ISD::EXPERIMENTAL_VP_SPLICE,
@@ -887,7 +887,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::VP_FDIV, ISD::VP_FNEG, ISD::VP_FABS,
ISD::VP_FMA, ISD::VP_REDUCE_FADD, ISD::VP_REDUCE_SEQ_FADD,
ISD::VP_REDUCE_FMIN, ISD::VP_REDUCE_FMAX, ISD::VP_MERGE,
- ISD::VP_SELECT, ISD::VP_SINT_TO_FP, ISD::VP_UINT_TO_FP,
+ ISD::VP_SELECT,
ISD::VP_SETCC, ISD::VP_FP_ROUND, ISD::VP_FP_EXTEND,
ISD::VP_SQRT,
ISD::VP_FCOPYSIGN, ISD::VP_IS_FPCLASS, ISD::VP_REDUCE_FMINIMUM,
@@ -975,9 +975,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
OtherVT, Expand);
}
- setOperationAction({ISD::VP_FP_TO_SINT, ISD::VP_FP_TO_UINT,
- ISD::VP_TRUNCATE, ISD::VP_SETCC},
- VT, Custom);
+ setOperationAction({ISD::VP_TRUNCATE, ISD::VP_SETCC}, VT, Custom);
setOperationAction(ISD::VECTOR_DEINTERLEAVE, VT, Custom);
setOperationAction(ISD::VECTOR_INTERLEAVE, VT, Custom);
@@ -1315,7 +1313,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::VP_MERGE, ISD::VP_SELECT, ISD::SELECT}, VT,
Custom);
setOperationAction(ISD::SELECT_CC, VT, Expand);
- setOperationAction({ISD::VP_SINT_TO_FP, ISD::VP_UINT_TO_FP}, VT, Custom);
setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::CONCAT_VECTORS,
ISD::INSERT_SUBVECTOR, ISD::EXTRACT_SUBVECTOR,
ISD::VECTOR_DEINTERLEAVE, ISD::VECTOR_INTERLEAVE,
@@ -1368,7 +1365,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::VP_MERGE, ISD::VP_SELECT, ISD::SELECT}, VT,
Custom);
setOperationAction(ISD::SELECT_CC, VT, Expand);
- setOperationAction({ISD::VP_SINT_TO_FP, ISD::VP_UINT_TO_FP}, VT, Custom);
setOperationAction({ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT,
ISD::CONCAT_VECTORS, ISD::INSERT_SUBVECTOR,
ISD::EXTRACT_SUBVECTOR, ISD::VECTOR_DEINTERLEAVE,
@@ -1540,9 +1536,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
ISD::OR, ISD::XOR},
VT, Custom);
- setOperationAction({ISD::VP_FP_TO_SINT, ISD::VP_FP_TO_UINT,
- ISD::VP_SETCC, ISD::VP_TRUNCATE},
- VT, Custom);
+ setOperationAction({ISD::VP_SETCC, ISD::VP_TRUNCATE}, VT, Custom);
setOperationAction(ISD::VP_MERGE, VT, Custom);
@@ -1680,8 +1674,6 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction(
{ISD::VP_MERGE, ISD::VP_SELECT, ISD::VSELECT, ISD::SELECT}, VT,
Custom);
- setOperationAction({ISD::VP_SINT_TO_FP, ISD::VP_UINT_TO_FP}, VT,
- Custom);
setOperationAction({ISD::LRINT, ISD::LLRINT}, VT, Custom);
setOperationAction({ISD::LROUND, ISD::LLROUND}, VT, Custom);
if (Subtarget.hasStdExtZfhmin()) {
@@ -7566,8 +7558,6 @@ static unsigned getRISCVVLOp(SDValue Op) {
VP_CASE(UMAX) // VP_UMAX
VP_CASE(FCOPYSIGN) // VP_FCOPYSIGN
VP_CASE(SETCC) // VP_SETCC
- VP_CASE(SINT_TO_FP) // VP_SINT_TO_FP
- VP_CASE(UINT_TO_FP) // VP_UINT_TO_FP
VP_CASE(BITREVERSE) // VP_BITREVERSE
VP_CASE(SADDSAT) // VP_SADDSAT
VP_CASE(UADDSAT) // VP_UADDSAT
@@ -7620,10 +7610,6 @@ static unsigned getRISCVVLOp(SDValue Op) {
return RISCVISD::VSEXT_VL;
case ISD::VP_ZERO_EXTEND:
return RISCVISD::VZEXT_VL;
- case ISD::VP_FP_TO_SINT:
- return RISCVISD::VFCVT_RTZ_X_F_VL;
- case ISD::VP_FP_TO_UINT:
- return RISCVISD::VFCVT_RTZ_XU_F_VL;
case ISD::FMINNUM:
case ISD::FMINIMUMNUM:
return RISCVISD::VFMIN_VL;
@@ -9001,45 +8987,6 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
case ISD::VP_FP_EXTEND:
case ISD::VP_FP_ROUND:
return lowerVectorFPExtendOrRoundLike(Op, DAG);
- case ISD::VP_SINT_TO_FP:
- case ISD::VP_UINT_TO_FP:
- if (Op.getValueType().isVector() &&
- ((Op.getValueType().getScalarType() == MVT::f16 &&
- (Subtarget.hasVInstructionsF16Minimal() &&
- !Subtarget.hasVInstructionsF16())) ||
- Op.getValueType().getScalarType() == MVT::bf16)) {
- if (isPromotedOpNeedingSplit(Op, Subtarget))
- return SplitVectorOp(Op, DAG);
- // int -> f32
- SDLoc DL(Op);
- MVT NVT =
- MVT::getVectorVT(MVT::f32, Op.getValueType().getVectorElementCount());
- auto NC = DAG.getNode(Op.getOpcode(), DL, NVT, Op->ops());
- // f32 -> [b]f16
- return DAG.getNode(ISD::FP_ROUND, DL, Op.getValueType(), NC,
- DAG.getIntPtrConstant(0, DL, /*isTarget=*/true));
- }
- [[fallthrough]];
- case ISD::VP_FP_TO_SINT:
- case ISD::VP_FP_TO_UINT:
- if (SDValue Op1 = Op.getOperand(0);
- Op1.getValueType().isVector() &&
- ((Op1.getValueType().getScalarType() == MVT::f16 &&
- (Subtarget.hasVInstructionsF16Minimal() &&
- !Subtarget.hasVInstructionsF16())) ||
- Op1.getValueType().getScalarType() == MVT::bf16)) {
- if (isPromotedOpNeedingSplit(Op1, Subtarget))
- return SplitVectorOp(Op, DAG);
- // [b]f16 -> f32
- SDLoc DL(Op);
- MVT NVT = MVT::getVectorVT(MVT::f32,
- Op1.getValueType().getVectorElementCount());
- SDValue WidenVec = DAG.getNode(ISD::FP_EXTEND, DL, NVT, Op1);
- // f32 -> int
- return DAG.getNode(Op.getOpcode(), DL, Op.getValueType(),
- {WidenVec, Op.getOperand(1), Op.getOperand(2)});
- }
- return lowerVPFPIntConvOp(Op, DAG);
case ISD::VP_SETCC:
if (isPromotedOpNeedingSplit(Op.getOperand(0), Subtarget))
return SplitVPOp(Op, DAG);
@@ -14097,140 +14044,6 @@ SDValue RISCVTargetLowering::lowerVPSetCCMaskOp(SDValue Op,
return convertFromScalableVector(VT, Result, DAG, Subtarget);
}
-// Lower Floating-Point/Integer Type-Convert VP SDNodes
-SDValue RISCVTargetLowering::lowerVPFPIntConvOp(SDValue Op,
- SelectionDAG &DAG) const {
- SDLoc DL(Op);
-
- SDValue Src = Op.getOperand(0);
- SDValue Mask = Op.getOperand(1);
- SDValue VL = Op.getOperand(2);
- unsigned RISCVISDOpc = getRISCVVLOp(Op);
-
- MVT DstVT = Op.getSimpleValueType();
- MVT SrcVT = Src.getSimpleValueType();
- if (DstVT.isFixedLengthVector()) {
- DstVT = getContainerForFixedLengthVector(DstVT);
- SrcVT = getContainerForFixedLengthVector(SrcVT);
- Src = convertToScalableVector(SrcVT, Src, DAG, Subtarget);
- MVT MaskVT = getMaskTypeFor(DstVT);
- Mask = convertToScalableVector(MaskVT, Mask, DAG, Subtarget);
- }
-
- unsigned DstEltSize = DstVT.getScalarSizeInBits();
- unsigned SrcEltSize = SrcVT.getScalarSizeInBits();
-
- SDValue Result;
- if (DstEltSize >= SrcEltSize) { // Single-width and widening conversion.
- if (SrcVT.isInteger()) {
- assert(DstVT.isFloatingPoint() && "Wrong input/output vector types");
-
- unsigned RISCVISDExtOpc = RISCVISDOpc == RISCVISD::SINT_TO_FP_VL
- ? RISCVISD::VSEXT_VL
- : RISCVISD::VZEXT_VL;
-
- // Do we need to do any pre-widening before converting?
- if (SrcEltSize == 1) {
- MVT IntVT = DstVT.changeVectorElementTypeToInteger();
- MVT XLenVT = Subtarget.getXLenVT();
- SDValue Zero = DAG.getConstant(0, DL, XLenVT);
- SDValue ZeroSplat = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, IntVT,
- DAG.getUNDEF(IntVT), Zero, VL);
- SDValue One = DAG.getSignedConstant(
- RISCVISDExtOpc == RISCVISD::VZEXT_VL ? 1 : -1, DL, XLenVT);
- SDValue OneSplat = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, IntVT,
- DAG.getUNDEF(IntVT), One, VL);
- Src = DAG.getNode(RISCVISD::VMERGE_VL, DL, IntVT, Src, OneSplat,
- ZeroSplat, DAG.getUNDEF(IntVT), VL);
- } else if (DstEltSize > (2 * SrcEltSize)) {
- // Widen before converting.
- MVT IntVT = MVT::getVectorVT(MVT::getIntegerVT(DstEltSize / 2),
- DstVT.getVectorElementCount());
- Src = DAG.getNode(RISCVISDExtOpc, DL, IntVT, Src, Mask, VL);
- }
-
- Result = DAG.getNode(RISCVISDOpc, DL, DstVT, Src, Mask, VL);
- } else {
- assert(SrcVT.isFloatingPoint() && DstVT.isInteger() &&
- "Wrong input/output vector types");
-
- // Convert f16 to f32 then convert f32 to i64.
- if (DstEltSize > (2 * SrcEltSize)) {
- assert(SrcVT.getVectorElementType() == MVT::f16 && "Unexpected type!");
- MVT InterimFVT =
- MVT::getVectorVT(MVT::f32, DstVT.getVectorElementCount());
- Src =
- DAG.getNode(RISCVISD::FP_EXTEND_VL, DL, InterimFVT, Src, Mask, VL);
- }
-
- Result = DAG.getNode(RISCVISDOpc, DL, DstVT, Src, Mask, VL);
- }
- } else { // Narrowing + Conversion
- if (SrcVT.isInteger()) {
- assert(DstVT.isFloatingPoint() && "Wrong input/output vector types");
- // First do a narrowing convert to an FP type half the size, then round
- // the FP type to a small FP type if needed.
-
- MVT InterimFVT = DstVT;
- if (SrcEltSize > (2 * DstEltSize)) {
- assert(SrcEltSize == (4 * DstEltSize) && "Unexpected types!");
- assert(DstVT.getVectorElementType() == MVT::f16 && "Unexpected type!");
- InterimFVT = MVT::getVectorVT(MVT::f32, DstVT.getVectorElementCount());
- }
-
- Result = DAG.getNode(RISCVISDOpc, DL, InterimFVT, Src, Mask, VL);
-
- if (InterimFVT != DstVT) {
- Src = Result;
- Result = DAG.getNode(RISCVISD::FP_ROUND_VL, DL, DstVT, Src, Mask, VL);
- }
- } else {
- assert(SrcVT.isFloatingPoint() && DstVT.isInteger() &&
- "Wrong input/output vector types");
- // First do a narrowing conversion to an integer half the size, then
- // truncate if needed.
-
- if (DstEltSize == 1) {
- // First convert to the same size integer, then convert to mask using
- // setcc.
- assert(SrcEltSize >= 16 && "Unexpected FP type!");
- MVT InterimIVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize),
- DstVT.getVectorElementCount());
- Result = DAG.getNode(RISCVISDOpc, DL, InterimIVT, Src, Mask, VL);
-
- // Compare the integer result to 0. The integer should be 0 or 1/-1,
- // otherwise the conversion was undefined.
- MVT XLenVT = Subtarget.getXLenVT();
- SDValue SplatZero = DAG.getConstant(0, DL, XLenVT);
- SplatZero = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, InterimIVT,
- DAG.getUNDEF(InterimIVT), SplatZero, VL);
- Result = DAG.getNode(RISCVISD::SETCC_VL, DL, DstVT,
- {Result, SplatZero, DAG.getCondCode(ISD::SETNE),
- DAG.getUNDEF(DstVT), Mask, VL});
- } else {
- MVT InterimIVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize / 2),
- DstVT.getVectorElementCount());
-
- Result = DAG.getNode(RISCVISDOpc, DL, InterimIVT, Src, Mask, VL);
-
- while (InterimIVT != DstVT) {
- SrcEltSize /= 2;
- Src = Result;
- InterimIVT = MVT::getVectorVT(MVT::getIntegerVT(SrcEltSize / 2),
- DstVT.getVectorElementCount());
- Result = DAG.getNode(RISCVISD::TRUNCATE_VECTOR_VL, DL, InterimIVT,
- Src, Mask, VL);
- }
- }
- }
- }
-
- MVT VT = Op.getSimpleValueType();
- if (!VT.isFixedLengthVector())
- return Result;
- return convertFromScalableVector(VT, Result, DAG, Subtarget);
-}
-
SDValue RISCVTargetLowering::lowerVPMergeMask(SDValue Op,
SelectionDAG &DAG) const {
SDLoc DL(Op);
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index 8d88aeb7ae3fc..1a53111bf0f85 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -552,7 +552,6 @@ class RISCVTargetLowering : public TargetLowering {
SDValue lowerVPMergeMask(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerVPSpliceExperimental(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerVPReverseExperimental(SDValue Op, SelectionDAG &DAG) const;
- SDValue lowerVPFPIntConvOp(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerVPStridedLoad(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerVPStridedStore(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerVPCttzElements(SDValue Op, SelectionDAG &DAG) const;
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
index 38c859a08c41b..edfbf77ab88a0 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h
@@ -386,8 +386,6 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
Intrinsic::vp_fmuladd,
Intrinsic::vp_fneg,
Intrinsic::vp_fpext,
- Intrinsic::vp_fptosi,
- Intrinsic::vp_fptoui,
Intrinsic::vp_fptrunc,
Intrinsic::vp_frem,
Intrinsic::vp_fshl,
@@ -425,7 +423,6 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
Intrinsic::vp_select,
Intrinsic::vp_sext,
Intrinsic::vp_shl,
- Intrinsic::vp_sitofp,
Intrinsic::vp_smax,
Intrinsic::vp_smin,
Intrinsic::vp_sqrt,
@@ -436,7 +433,6 @@ class RISCVTTIImpl final : public BasicTTIImplBase<RISCVTTIImpl> {
Intrinsic::vp_trunc,
Intrinsic::vp_uadd_sat,
Intrinsic::vp_udiv,
- Intrinsic::vp_uitofp,
Intrinsic::vp_umax,
Intrinsic::vp_umin,
Intrinsic::vp_urem,
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll
index b46a0b0e5f55b..223e5f6ff5af7 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp-mask.ll
@@ -7,18 +7,17 @@
define <4 x i1> @vfptosi_v4i1_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) {
; ZVFH-LABEL: vfptosi_v4i1_v4f16:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFH-NEXT: vfcvt.rtz.x.f.v v8, v8, v0.t
-; ZVFH-NEXT: vmsne.vi v0, v8, 0, v0.t
+; ZVFH-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; ZVFH-NEXT: vfncvt.rtz.x.f.w v9, v8
+; ZVFH-NEXT: vmsne.vi v0, v9, 0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfptosi_v4i1_v4f16:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v8, v9, v0.t
-; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0, v0.t
+; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9
+; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0
; ZVFHMIN-NEXT: ret
%v = call <4 x i1> @llvm.vp.fptosi.v4i1.v4f16(<4 x half> %va, <4 x i1> %m, i32 %evl)
ret <4 x i1> %v
@@ -27,17 +26,16 @@ define <4 x i1> @vfptosi_v4i1_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %ev
define <4 x i1> @vfptosi_v4i1_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) {
; ZVFH-LABEL: vfptosi_v4i1_v4f16_unmasked:
; ZVFH: # %bb.0:
-; ZVFH-NEXT: vsetvli zero, a0, e16, mf2, ta, ma
-; ZVFH-NEXT: vfcvt.rtz.x.f.v v8, v8
-; ZVFH-NEXT: vmsne.vi v0, v8, 0
+; ZVFH-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
+; ZVFH-NEXT: vfncvt.rtz.x.f.w v9, v8
+; ZVFH-NEXT: vmsne.vi v0, v9, 0
; ZVFH-NEXT: ret
;
; ZVFHMIN-LABEL: vfptosi_v4i1_v4f16_unmasked:
; ZVFHMIN: # %bb.0:
; ZVFHMIN-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
; ZVFHMIN-NEXT: vfwcvt.f.f.v v9, v8
-; ZVFHMIN-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; ZVFHMIN-NEXT: vfcvt.rtz.x.f.v v8, v9
+; ZVFHMIN-NEXT: vfncvt.rtz.x.f.w v8, v9
; ZVFHMIN-NEXT: vmsne.vi v0, v8, 0
; ZVFHMIN-NEXT: ret
%v = call <4 x i1> @llvm.vp.fptosi.v4i1.v4f16(<4 x half> %va, <4 x i1> splat (i1 true), i32 %evl)
@@ -47,9 +45,9 @@ define <4 x i1> @vfptosi_v4i1_v4f16_unmasked(<4 x half> %va, i32 zeroext %evl) {
define <4 x i1> @vfptosi_v4i1_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptosi_v4i1_v4f32:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8, v0.t
-; CHECK-NEXT: vmsne.vi v0, v8, 0, v0.t
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmsne.vi v0, v9, 0
; CHECK-NEXT: ret
%v = call <4 x i1> @llvm.vp.fptosi.v4i1.v4f32(<4 x float> %va, <4 x i1> %m, i32 %evl)
ret <4 x i1> %v
@@ -58,9 +56,9 @@ define <4 x i1> @vfptosi_v4i1_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %e
define <4 x i1> @vfptosi_v4i1_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl) {
; CHECK-LABEL: vfptosi_v4i1_v4f32_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
-; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
-; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
+; CHECK-NEXT: vfncvt.rtz.x.f.w v9, v8
+; CHECK-NEXT: vmsne.vi v0, v9, 0
; CHECK-NEXT: ret
%v = call <4 x i1> @llvm.vp.fptosi.v4i1.v4f32(<4 x float> %va, <4 x i1> splat (i1 true), i32 %evl)
ret <4 x i1> %v
@@ -69,10 +67,9 @@ define <4 x i1> @vfptosi_v4i1_v4f32_unmasked(<4 x float> %va, i32 zeroext %evl)
define <4 x i1> @vfptosi_v4i1_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %evl) {
; CHECK-LABEL: vfptosi_v4i1_v4f64:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8, v0.t
-; CHECK-NEXT: vmsne.vi v10, v8, 0, v0.t
-; CHECK-NEXT: vmv1r.v v0, v10
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: ret
%v = call <4 x i1> @llvm.vp.fptosi.v4i1.v4f64(<4 x double> %va, <4 x i1> %m, i32 %evl)
ret <4 x i1> %v
@@ -81,9 +78,9 @@ define <4 x i1> @vfptosi_v4i1_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %
define <4 x i1> @vfptosi_v4i1_v4f64_unmasked(<4 x double> %va, i32 zeroext %evl) {
; CHECK-LABEL: vfptosi_v4i1_v4f64_unmasked:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma
-; CHECK-NEXT: vfcvt.rtz.x.f.v v8, v8
-; CHECK-NEXT: vmsne.vi v0, v8, 0
+; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
+; CHECK-NEXT: vfncvt.rtz.x.f.w v10, v8
+; CHECK-NEXT: vmsne.vi v0, v10, 0
; CHECK-NEXT: ret
%v = call <4 x i1> @llvm.vp.fptosi.v4i1.v4f64(<4 x double> %va, <4 x i1> splat (i1 true), i32 %evl)
ret <4 x i1> %v
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
index 96eda109e1c70..00b07f51cba59 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fptosi-vp.ll
@@ -7,8 +7,8 @@
define <4 x i7> @vfptosi_v4i7_v4f16(<4 x h...
[truncated]
|
You can test this locally with the following command:git-clang-format --diff origin/main HEAD --extensions cpp,h -- llvm/lib/Target/RISCV/RISCVISelLowering.cpp llvm/lib/Target/RISCV/RISCVISelLowering.h llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h --diff_from_common_commit
View the diff from clang-format here.diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index a472dffd9..c250f5493 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -866,32 +866,68 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
setOperationAction({ISD::INTRINSIC_W_CHAIN, ISD::INTRINSIC_VOID},
MVT::Other, Custom);
- static const unsigned IntegerVPOps[] = {
- ISD::VP_ADD, ISD::VP_SUB, ISD::VP_MUL,
- ISD::VP_SDIV, ISD::VP_UDIV, ISD::VP_SREM,
- ISD::VP_UREM, ISD::VP_AND, ISD::VP_OR,
- ISD::VP_XOR, ISD::VP_SRA, ISD::VP_SRL,
- ISD::VP_SHL, ISD::VP_REDUCE_ADD, ISD::VP_REDUCE_AND,
- ISD::VP_REDUCE_OR, ISD::VP_REDUCE_XOR, ISD::VP_REDUCE_SMAX,
- ISD::VP_REDUCE_SMIN, ISD::VP_REDUCE_UMAX, ISD::VP_REDUCE_UMIN,
- ISD::VP_MERGE, ISD::VP_SELECT, ISD::VP_SETCC,
- ISD::VP_SIGN_EXTEND,
- ISD::VP_ZERO_EXTEND, ISD::VP_TRUNCATE, ISD::VP_SMIN,
- ISD::VP_SMAX, ISD::VP_UMIN, ISD::VP_UMAX,
- ISD::VP_ABS, ISD::EXPERIMENTAL_VP_REVERSE, ISD::EXPERIMENTAL_VP_SPLICE,
- ISD::VP_SADDSAT, ISD::VP_UADDSAT, ISD::VP_SSUBSAT,
- ISD::VP_USUBSAT, ISD::VP_CTTZ_ELTS, ISD::VP_CTTZ_ELTS_ZERO_UNDEF};
-
- static const unsigned FloatingPointVPOps[] = {
- ISD::VP_FADD, ISD::VP_FSUB, ISD::VP_FMUL,
- ISD::VP_FDIV, ISD::VP_FNEG, ISD::VP_FABS,
- ISD::VP_FMA, ISD::VP_REDUCE_FADD, ISD::VP_REDUCE_SEQ_FADD,
- ISD::VP_REDUCE_FMIN, ISD::VP_REDUCE_FMAX, ISD::VP_MERGE,
- ISD::VP_SELECT,
- ISD::VP_SETCC, ISD::VP_FP_ROUND, ISD::VP_FP_EXTEND,
- ISD::VP_SQRT,
- ISD::VP_FCOPYSIGN, ISD::VP_IS_FPCLASS, ISD::VP_REDUCE_FMINIMUM,
- ISD::VP_REDUCE_FMAXIMUM};
+ static const unsigned IntegerVPOps[] = {ISD::VP_ADD,
+ ISD::VP_SUB,
+ ISD::VP_MUL,
+ ISD::VP_SDIV,
+ ISD::VP_UDIV,
+ ISD::VP_SREM,
+ ISD::VP_UREM,
+ ISD::VP_AND,
+ ISD::VP_OR,
+ ISD::VP_XOR,
+ ISD::VP_SRA,
+ ISD::VP_SRL,
+ ISD::VP_SHL,
+ ISD::VP_REDUCE_ADD,
+ ISD::VP_REDUCE_AND,
+ ISD::VP_REDUCE_OR,
+ ISD::VP_REDUCE_XOR,
+ ISD::VP_REDUCE_SMAX,
+ ISD::VP_REDUCE_SMIN,
+ ISD::VP_REDUCE_UMAX,
+ ISD::VP_REDUCE_UMIN,
+ ISD::VP_MERGE,
+ ISD::VP_SELECT,
+ ISD::VP_SETCC,
+ ISD::VP_SIGN_EXTEND,
+ ISD::VP_ZERO_EXTEND,
+ ISD::VP_TRUNCATE,
+ ISD::VP_SMIN,
+ ISD::VP_SMAX,
+ ISD::VP_UMIN,
+ ISD::VP_UMAX,
+ ISD::VP_ABS,
+ ISD::EXPERIMENTAL_VP_REVERSE,
+ ISD::EXPERIMENTAL_VP_SPLICE,
+ ISD::VP_SADDSAT,
+ ISD::VP_UADDSAT,
+ ISD::VP_SSUBSAT,
+ ISD::VP_USUBSAT,
+ ISD::VP_CTTZ_ELTS,
+ ISD::VP_CTTZ_ELTS_ZERO_UNDEF};
+
+ static const unsigned FloatingPointVPOps[] = {ISD::VP_FADD,
+ ISD::VP_FSUB,
+ ISD::VP_FMUL,
+ ISD::VP_FDIV,
+ ISD::VP_FNEG,
+ ISD::VP_FABS,
+ ISD::VP_FMA,
+ ISD::VP_REDUCE_FADD,
+ ISD::VP_REDUCE_SEQ_FADD,
+ ISD::VP_REDUCE_FMIN,
+ ISD::VP_REDUCE_FMAX,
+ ISD::VP_MERGE,
+ ISD::VP_SELECT,
+ ISD::VP_SETCC,
+ ISD::VP_FP_ROUND,
+ ISD::VP_FP_EXTEND,
+ ISD::VP_SQRT,
+ ISD::VP_FCOPYSIGN,
+ ISD::VP_IS_FPCLASS,
+ ISD::VP_REDUCE_FMINIMUM,
+ ISD::VP_REDUCE_FMAXIMUM};
static const unsigned IntegerVecReduceOps[] = {
ISD::VECREDUCE_ADD, ISD::VECREDUCE_AND, ISD::VECREDUCE_OR,
|
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Part of the work to remove trivial VP intrinsics from the RISC-V backend, see https://discourse.llvm.org/t/rfc-remove-codegen-support-for-trivial-vp-intrinsics-in-the-risc-v-backend/87999
This splits off 4 intrinsics from #179622.