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[sw,multitop] Port spi_device_passthrough and spi_host_testutils to DT #6045

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[sw,multitop] Port spi_device_passthrough and spi_host_testutils to DT

[sw,multitop] Port spi_device_passthrough and spi_host_testutils to DT #6045

Triggered via pull request February 14, 2025 16:15
@AlexJones0AlexJones0
synchronize #26284
AlexJones0:dt_spi_passthrough
Status Cancelled
Total duration 11m 59s
Artifacts 2

ci.yml

on: pull_request
Lint (quick)
3m 44s
Lint (quick)
Earl Grey for CW310 Hyperdebug  /  Build bitstream
0s
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW310  /  Build bitstream
0s
Earl Grey for CW310 / Build bitstream
Earl Grey for CW340  /  Build bitstream
0s
Earl Grey for CW340 / Build bitstream
Lint (slow)
7m 44s
Lint (slow)
Build documentation
5m 40s
Build documentation
Airgapped build
7m 55s
Airgapped build
Verible lint
1m 6s
Verible lint
Run OTBN smoke Test
2m 35s
Run OTBN smoke Test
Run OTBN crypto tests
2m 37s
Run OTBN crypto tests
Verilated English Breakfast
3m 53s
Verilated English Breakfast
Verilated Earl Grey
7m 54s
Verilated Earl Grey
CW305's Bitstream
2m 50s
CW305's Bitstream
Build Docker Containers
2m 24s
Build Docker Containers
Build and test software
6m 16s
Build and test software
Build and test Darjeeling software
3m 50s
Build and test Darjeeling software
QEMU smoketest
2m 37s
QEMU smoketest
CW310 Manufacturing Tests  /  FPGA test
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CW310 SiVal ROM_EXT Tests  /  FPGA test
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
CW310 SiVal Tests / FPGA test
Hyper310 ROM_EXT Tests  /  FPGA test
Hyper310 ROM_EXT Tests / FPGA test
CW310 ROM Tests  /  FPGA test
CW310 ROM Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
CW310 Test ROM Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
CW340 Manufacturing Tests / FPGA test
CW340 ROM Tests  /  FPGA test
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
CW340 SiVal Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
CW340 Test ROM Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
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Verify FPGA jobs
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19 errors
Verilated English Breakfast
Process completed with exit code 1.
Earl Grey for CW340 / Build bitstream
Canceling since a higher priority waiting request for 'CI-refs/pull/26284/merge' exists
Earl Grey for CW310 / Build bitstream
Canceling since a higher priority waiting request for 'CI-refs/pull/26284/merge' exists
Earl Grey for CW310 Hyperdebug / Build bitstream
Canceling since a higher priority waiting request for 'CI-refs/pull/26284/merge' exists
Lint (slow)
Canceling since a higher priority waiting request for 'CI-refs/pull/26284/merge' exists
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Some target names have banned characters.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
The operation was canceled.
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Verilated Earl Grey
Canceling since a higher priority waiting request for 'CI-refs/pull/26284/merge' exists
Verilated Earl Grey
The operation was canceled.
Airgapped build
Canceling since a higher priority waiting request for 'CI-refs/pull/26284/merge' exists
Airgapped build
The operation was canceled.
Build and test software
Canceling since a higher priority waiting request for 'CI-refs/pull/26284/merge' exists
Build and test software
The operation was canceled.

Artifacts

Produced during runtime
Name Size
chip_englishbreakfast_cw305
1.38 MB
verilated_englishbreakfast
7.05 MB