[acrc, dv] Create initial DV environment

- Use the following uvmdvgen command:
`util/uvmdvgen/uvmdvgen.py ac_range_check -e -c -hr -hi -ha -ea tl_csr
tl_unfilt tl_filt -eo hw/top_darjeeling/ip_autogen/ac_range_check`
- Adjust the generated files
- Instanciate the DUT into the TB top module
/!\ The generated files are not functional yet, it doesn't even compile

Signed-off-by: Martin Velay <[email protected]>

hw/top_darjeeling/ip_autogen/ac_range_check/data/ac_range_check_testplan.hjson

@@ -0,0 +1,39 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+  name: "ac_range_check"
+  import_testplans: ["hw/dv/tools/dvsim/testplans/csr_testplan.hjson",
+                     "hw/dv/tools/dvsim/testplans/mem_testplan.hjson",  // TODO MVy needed?
+                     "hw/dv/tools/dvsim/testplans/intr_test_testplan.hjson",
+                     "hw/dv/tools/dvsim/testplans/tl_device_access_types_testplan.hjson"]
+  testpoints: [
+    {
+      name: smoke
+      desc: '''
+            Smoke test accessing a major datapath within the ac_range_check.
+
+            **Stimulus**:
+            - TBD
+
+            **Checks**:
+            - TBD
+            '''
+      stage: V1
+      tests: ["ac_range_check_smoke"]
+    }
+    {
+      name: feature1
+      desc: '''Add more test entries here like above.'''
+      stage: V1
+      tests: []
+    }
+  ]
+
+  covergroups: [
+    {
+      name: ac_range_check_feature_cg
+      desc: '''Describe the functionality covered by this covergroup.'''
+    }
+  ]
+}

hw/top_darjeeling/ip_autogen/ac_range_check/doc/dv/index.md

@@ -0,0 +1,126 @@
+---
+title: "AC_RANGE_CHECK DV document"
+---
+
+<!-- Copy this file to hw/ip/ac_range_check/doc/dv/index.md and make changes as needed.
+For convenience 'ac_range_check' in the document can be searched and replaced easily with the
+desired IP (with case sensitivity!). Also, use the testbench block diagram
+located at OpenTitan team drive / 'design verification'
+as a starting point and modify it to reflect your ac_range_check testbench and save it
+to hw/ip/ac_range_check/doc/dv/tb.svg. It should get linked and rendered under the block
+diagram section below. Please update / modify / remove sections below as
+applicable. Once done, remove this comment before making a PR. -->
+
+## Goals
+* **DV**
+  * Verify all AC_RANGE_CHECK IP features by running dynamic simulations with a SV/UVM based testbench
+  * Develop and run all tests based on the [testplan](#testplan) below towards closing code and functional coverage on the IP and all of its sub-modules
+* **FPV**
+  * Verify TileLink device protocol compliance with an SVA based testbench
+
+## Current status
+* [Design & verification stage]({{< relref "hw" >}})
+  * [HW development stages]({{< relref "doc/project/development_stages" >}})
+* [Simulation results](https://reports.opentitan.org/hw/ip/ac_range_check/dv/latest/report.html)
+
+## Design features
+For detailed information on AC_RANGE_CHECK design features, please see the [AC_RANGE_CHECK HWIP technical specification]({{< relref "hw/ip/ac_range_check/doc" >}}).
+
+## Testbench architecture
+AC_RANGE_CHECK testbench has been constructed based on the [CIP testbench architecture]({{< relref "hw/dv/sv/cip_lib/doc" >}}).
+
+### Block diagram
+![Block diagram](tb.svg)
+
+### Top level testbench
+The top level testbench is located at `hw/ip/ac_range_check/dv/tb.sv`.
+It instantiates the AC_RANGE_CHECK DUT module `hw/ip/ac_range_check/rtl/ac_range_check.sv`.
+In addition, it instantiates the following interfaces, connects them to the DUT and sets their handle into `uvm_config_db`:
+* [Clock and reset interface]({{< relref "hw/dv/sv/common_ifs" >}})
+* [TileLink host interface]({{< relref "hw/dv/sv/tl_agent/doc" >}})
+* AC_RANGE_CHECK IOs
+* Interrupts ([`pins_if`]({{< relref "hw/dv/sv/common_ifs" >}}))
+* Alerts ([`alert_esc_if`]({{< relref "hw/dv/sv/alert_esc_agent/doc" >}}))
+
+### Common DV utility components
+The following utilities provide generic helper tasks and functions to perform activities that are common across the project:
+* [dv_utils_pkg]({{< relref "hw/dv/sv/dv_utils/doc" >}})
+* [csr_utils_pkg]({{< relref "hw/dv/sv/csr_utils/doc" >}})
+
+### Compile-time configurations
+[list compile time configurations, if any and what are they used for]
+
+### Global types & methods
+All common types and methods defined at the package level can be found in
+`ac_range_check_env_pkg`. Some of them in use are:
+```systemverilog
+[list a few parameters, types & methods; no need to mention all]
+```
+### TL_CSR Agent
+The AC_RANGE_CHECK testbench instantiates (already handled in CIP base env) [tl_agent]({{< relref "hw/dv/sv/tl_agent/doc" >}}).
+This provides the ability to drive and independently monitor random traffic via the TL host interface into the AC_RANGE_CHECK device.
+
+### Alert_agents
+AC_RANGE_CHECK testbench instantiates (already handled in CIP base env) [alert_agents]({{< relref "hw/dv/sv/alert_esc_agent/doc" >}}):
+[list alert names].
+The alert_agents provide the ability to drive and independently monitor alert handshakes via alert interfaces in AC_RANGE_CHECK device.
+
+###  TL_UNFILT Agent
+[Describe here or add link to its README]
+
+###  TL_FILT Agent
+[Describe here or add link to its README]
+
+### UVC/agent 1
+[Describe here or add link to its README]
+
+### UVC/agent 2
+[Describe here or add link to its README]
+
+### UVM RAL Model
+The AC_RANGE_CHECK RAL model is created with the [`ralgen`]({{< relref "hw/dv/tools/ralgen/doc" >}}) FuseSoC generator script automatically when the simulation is at the build stage.
+
+It can be created manually by invoking [`regtool`]({{< relref "util/reggen/doc" >}}):
+
+### Reference models
+[Describe reference models in use if applicable, example: SHA256/HMAC]
+
+### Stimulus strategy
+#### Test sequences
+The test sequences reside in `hw/ip/ac_range_check/dv/env/seq_lib`.
+All test sequences are extended from `ac_range_check_base_vseq`, which is extended from `cip_base_vseq` and serves as a starting point.
+It provides commonly used handles, variables, functions and tasks that the test sequences can simple use / call.
+Some of the most commonly used tasks / functions are as follows:
+* task 1:
+* task 2:
+
+#### Functional coverage
+To ensure high quality constrained random stimulus, it is necessary to develop a functional coverage model.
+The following covergroups have been developed to prove that the test intent has been adequately met:
+* cg1:
+* cg2:
+
+### Self-checking strategy
+#### Scoreboard
+The `ac_range_check_scoreboard` is primarily used for end to end checking.
+It creates the following analysis ports to retrieve the data monitored by corresponding interface agents:
+* analysis port1:
+* analysis port2:
+<!-- explain inputs monitored, flow of data and outputs checked -->
+
+#### Assertions
+* TLUL assertions: The `tb/ac_range_check_bind.sv` file binds the `tlul_assert` [assertions]({{< relref "hw/ip/tlul/doc/TlulProtocolChecker.md" >}}) to the IP to ensure TileLink interface protocol compliance.
+* Unknown checks on DUT outputs: The RTL has assertions to ensure all outputs are initialized to known values after coming out of reset.
+* assert prop 1:
+* assert prop 2:
+
+## Building and running tests
+We are using our in-house developed [regression tool]({{< relref "hw/dv/tools/doc" >}}) for building and running our tests and regressions.
+Please take a look at the link for detailed information on the usage, capabilities, features and known issues.
+Here's how to run a smoke test:
+```console
+$ $REPO_TOP/util/dvsim/dvsim.py $REPO_TOP/hw/ip/ac_range_check/dv/ac_range_check_sim_cfg.hjson -i ac_range_check_smoke
+```
+
+## Testplan
+[Testplan](../../data/ac_range_check_testplan.hjson)

hw/top_darjeeling/ip_autogen/ac_range_check/dv/ac_range_check_sim.core

@@ -0,0 +1,29 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:ac_range_check_sim:0.1"
+description: "AC_RANGE_CHECK DV sim target"
+filesets:
+  files_rtl:
+    depend:
+      - lowrisc:ip:ac_range_check
+
+  files_dv:
+    depend:
+      - lowrisc:dv:ac_range_check_test
+      - lowrisc:dv:ac_range_check_sva
+    files:
+      - tb.sv
+    file_type: systemVerilogSource
+
+targets:
+  sim: &sim_target
+    toplevel: tb
+    filesets:
+      - files_rtl
+      - files_dv
+    default_tool: vcs
+
+  lint:
+    <<: *sim_target

hw/top_darjeeling/ip_autogen/ac_range_check/dv/ac_range_check_sim_cfg.hjson

@@ -0,0 +1,64 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+{
+  // Name of the sim cfg - typically same as the name of the DUT.
+  name: ac_range_check
+
+  // Top level dut name (sv module).
+  dut: ac_range_check
+
+  // Top level testbench name (sv module).
+  tb: tb
+
+  // Simulator used to sign off this block
+  tool: vcs
+
+  // Fusesoc core file used for building the file list.
+  fusesoc_core: lowrisc:dv:ac_range_check_sim:0.1
+
+  // Testplan hjson file.
+  testplan: "{proj_root}/hw/ip/ac_range_check/data/ac_range_check_testplan.hjson"
+
+  // RAL spec - used to generate the RAL model.
+  ral_spec: "{proj_root}/hw/ip/ac_range_check/data/ac_range_check.hjson"
+
+  // Import additional common sim cfg files.
+  import_cfgs: [// Project wide common sim cfg file
+                "{proj_root}/hw/dv/tools/dvsim/common_sim_cfg.hjson",
+                // Common CIP test lists
+                "{proj_root}/hw/dv/tools/dvsim/tests/csr_tests.hjson",
+                "{proj_root}/hw/dv/tools/dvsim/tests/mem_tests.hjson",  // TODO MVy needed?
+                "{proj_root}/hw/dv/tools/dvsim/tests/intr_test.hjson",
+                "{proj_root}/hw/dv/tools/dvsim/tests/alert_test.hjson",
+                "{proj_root}/hw/dv/tools/dvsim/tests/tl_access_tests.hjson",
+                "{proj_root}/hw/dv/tools/dvsim/tests/stress_tests.hjson"]
+
+  // Add additional tops for simulation.
+  sim_tops: ["ac_range_check_bind"]
+
+  // Default iterations for all tests - each test entry can override this.
+  reseed: 50
+
+  // Default UVM test and seq class name.
+  uvm_test: ac_range_check_base_test
+  uvm_test_seq: ac_range_check_base_vseq
+
+  // List of test specifications.
+  tests: [
+    {
+      name: ac_range_check_smoke
+      uvm_test_seq: ac_range_check_smoke_vseq
+    }
+
+    // TODO: add more tests here
+  ]
+
+  // List of regressions.
+  regressions: [
+    {
+      name: smoke
+      tests: ["ac_range_check_smoke"]
+    }
+  ]
+}

hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env.core

@@ -0,0 +1,40 @@
+CAPI=2:
+# Copyright lowRISC contributors (OpenTitan project).
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+name: "lowrisc:dv:ac_range_check_env:0.1"
+description: "AC_RANGE_CHECK DV UVM environment"
+filesets:
+  files_dv:
+    depend:
+      - lowrisc:dv:ralgen
+      - lowrisc:dv:cip_lib
+      - lowrisc:dv:tl_agent
+      - lowrisc:dv:dv_base_reg
+    files:
+      - ac_range_check_env_pkg.sv
+      - ac_range_check_ral_pkg.sv
+      - ac_range_check_env_cfg.sv: {is_include_file: true}
+      - ac_range_check_env_cov.sv: {is_include_file: true}
+      - ac_range_check_virtual_sequencer.sv: {is_include_file: true}
+      - ac_range_check_scoreboard.sv: {is_include_file: true}
+      - ac_range_check_env.sv: {is_include_file: true}
+      - seq_lib/ac_range_check_vseq_list.sv: {is_include_file: true}
+      - seq_lib/ac_range_check_base_vseq.sv: {is_include_file: true}
+      - seq_lib/ac_range_check_common_vseq.sv: {is_include_file: true}
+      - seq_lib/ac_range_check_smoke_vseq.sv: {is_include_file: true}
+    file_type: systemVerilogSource
+
+generate:
+  ral:
+    generator: ralgen
+    parameters:
+      name: ac_range_check
+      ip_hjson: ../../data/ac_range_check.hjson
+
+targets:
+  default:
+    filesets:
+      - files_dv
+    generate:
+      - ral

hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env.sv

@@ -0,0 +1,56 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class ac_range_check_env extends cip_base_env #(
+    .CFG_T              (ac_range_check_env_cfg),
+    .COV_T              (ac_range_check_env_cov),
+    .VIRTUAL_SEQUENCER_T(ac_range_check_virtual_sequencer),
+    .SCOREBOARD_T       (ac_range_check_scoreboard)
+  );
+  `uvm_component_utils(ac_range_check_env)
+
+  tl_agent tl_csr_agent;
+  tl_agent tl_unfilt_agent;
+  tl_agent tl_filt_agent;
+
+  `uvm_component_new
+
+  function void build_phase(uvm_phase phase);
+    super.build_phase(phase);
+
+    // Create CSR TL agent
+    tl_csr_agent = tl_agent::type_id::create("tl_csr_agent", this);
+    uvm_config_db#(tl_agent_cfg)::set(this, "tl_csr_agent*", "cfg", cfg.tl_csr_agent_cfg);
+    cfg.tl_csr_agent_cfg.en_cov = cfg.en_cov;
+
+    // Create Unfiltered TL agent
+    tl_unfilt_agent = tl_agent::type_id::create("tl_unfilt_agent", this);
+    uvm_config_db#(tl_agent_cfg)::set(this, "tl_unfilt_agent*", "cfg", cfg.tl_unfilt_agent_cfg);
+    cfg.tl_unfilt_agent_cfg.en_cov = cfg.en_cov;
+
+    // Create Fltered TL agent
+    tl_filt_agent = tl_agent::type_id::create("tl_filt_agent", this);
+    uvm_config_db#(tl_agent_cfg)::set(this, "tl_filt_agent*", "cfg", cfg.tl_filt_agent_cfg);
+    cfg.tl_filt_agent_cfg.en_cov = cfg.en_cov;
+  endfunction
+
+  function void connect_phase(uvm_phase phase);
+    super.connect_phase(phase);
+    if (cfg.en_scb) begin
+      tl_csr_agent.monitor.analysis_port.connect(scoreboard.tl_csr_fifo.analysis_export);
+      tl_unfilt_agent.monitor.analysis_port.connect(scoreboard.tl_unfilt_fifo.analysis_export);
+      tl_filt_agent.monitor.analysis_port.connect(scoreboard.tl_filt_fifo.analysis_export);
+    end
+    if (cfg.is_active && cfg.tl_csr_agent_cfg.is_active) begin
+      virtual_sequencer.tl_csr_sqr = tl_csr_agent.sequencer;
+    end
+    if (cfg.is_active && cfg.tl_unfilt_agent_cfg.is_active) begin
+      virtual_sequencer.tl_unfilt_sqr = tl_unfilt_agent.sequencer;
+    end
+    if (cfg.is_active && cfg.tl_filt_agent_cfg.is_active) begin
+      virtual_sequencer.tl_filt_sqr = tl_filt_agent.sequencer;
+    end
+  endfunction
+
+endclass

hw/top_darjeeling/ip_autogen/ac_range_check/dv/env/ac_range_check_env_cfg.sv

@@ -0,0 +1,39 @@
+// Copyright lowRISC contributors (OpenTitan project).
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+
+class ac_range_check_env_cfg extends cip_base_env_cfg #(.RAL_T(ac_range_check_reg_block));
+
+  // Ext component cfgs
+  rand tl_agent_cfg tl_csr_agent_cfg;
+  rand tl_agent_cfg tl_unfilt_agent_cfg;
+  rand tl_agent_cfg tl_filt_agent_cfg;
+
+  `uvm_object_utils_begin(ac_range_check_env_cfg)
+    `uvm_field_object(tl_csr_agent_cfg, UVM_DEFAULT)
+    `uvm_field_object(tl_unfilt_agent_cfg, UVM_DEFAULT)
+    `uvm_field_object(tl_filt_agent_cfg, UVM_DEFAULT)
+  `uvm_object_utils_end
+
+  `uvm_object_new
+
+  virtual function void initialize(bit [31:0] csr_base_addr = '1);
+    list_of_alerts = ac_range_check_env_pkg::LIST_OF_ALERTS;
+    super.initialize(csr_base_addr);
+    // Create tl_csr agent config obj
+    tl_csr_agent_cfg = tl_agent_cfg::type_id::create("tl_csr_agent_cfg");
+    // Create tl_unfilt agent config obj
+    tl_unfilt_agent_cfg = tl_agent_cfg::type_id::create("tl_unfilt_agent_cfg");
+    // Create tl_filt agent config obj
+    tl_filt_agent_cfg = tl_agent_cfg::type_id::create("tl_filt_agent_cfg");
+
+    // Set num_interrupts
+    begin
+      uvm_reg rg = ral.get_reg_by_name("intr_state");
+      if (rg != null) begin
+        num_interrupts = ral.intr_state.get_n_used_bits();
+      end
+    end
+  endfunction
+
+endclass