[topgen] All RACL configs are relative to the top HJSON

Signed-off-by: Robert Schilling <[email protected]>
lowRISC · Feb 4, 2025 · d8fb30e · d8fb30e
1 parent 56af8ac
commit d8fb30e
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Showing 3 changed files with 15 additions and 15 deletions.
diff --git a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson
@@ -13,7 +13,7 @@
   type: top
   rnd_cnst_seed: 1017106219537032642877583828875051302543807092889754935647094601236425074047
   datawidth: "32"
-  racl_config: top_darjeeling/data/racl/racl.hjson
+  racl_config: racl/racl.hjson
   power:
   {
     domains:

diff --git a/hw/top_darjeeling/data/top_darjeeling.hjson b/hw/top_darjeeling/data/top_darjeeling.hjson
@@ -16,7 +16,7 @@
   datawidth: "32",
 
   // Enable RACL on Darjeeling based on the following configuration
-  racl_config: 'top_darjeeling/data/racl/racl.hjson'
+  racl_config: 'racl/racl.hjson'
 
   // Power information for the design
   power: {
@@ -879,7 +879,7 @@
         soc:  {soc_mbx: "0x01465000"},
       },
       racl_mappings: {
-        soc: 'top_darjeeling/data/racl/all_rd_wr_mapping.hjson'
+        soc: 'racl/all_rd_wr_mapping.hjson'
       }
     },
     { name: "mbx1",
@@ -892,7 +892,7 @@
         soc:  {soc_mbx: "0x01465100"},
       },
       racl_mappings: {
-        soc: 'top_darjeeling/data/racl/all_rd_wr_mapping.hjson'
+        soc: 'racl/all_rd_wr_mapping.hjson'
       }
     },
     { name: "mbx2",
@@ -905,7 +905,7 @@
         soc:  {soc_mbx: "0x01465200"},
       },
       racl_mappings: {
-        soc: 'top_darjeeling/data/racl/all_rd_wr_mapping.hjson'
+        soc: 'racl/all_rd_wr_mapping.hjson'
       }
     },
     { name: "mbx3",
@@ -928,7 +928,7 @@
         soc:  {soc_mbx: "0x01465400"},
       },
       racl_mappings: {
-        soc: 'top_darjeeling/data/racl/all_rd_wr_mapping.hjson'
+        soc: 'racl/all_rd_wr_mapping.hjson'
       }
     },
     { name: "mbx5",
@@ -941,7 +941,7 @@
         soc:  {soc_mbx: "0x01465500"},
       },
       racl_mappings: {
-        soc: 'top_darjeeling/data/racl/all_rd_wr_mapping.hjson'
+        soc: 'racl/all_rd_wr_mapping.hjson'
       }
     },
     { name: "mbx6",
@@ -964,7 +964,7 @@
         soc:  {soc_dbg: "0x1000"},
       },
       racl_mappings: {
-        soc: 'top_darjeeling/data/racl/all_rd_wr_mapping.hjson'
+        soc: 'racl/all_rd_wr_mapping.hjson'
       }
     },
     { name: "mbx_pcie0",
@@ -977,7 +977,7 @@
         soc:  {soc_mbx: "0x01460100"},
       },
       racl_mappings: {
-        soc: 'top_darjeeling/data/racl/soc_rot_mapping.hjson'
+        soc: 'racl/soc_rot_mapping.hjson'
       }
     },
     { name: "mbx_pcie1",
@@ -990,7 +990,7 @@
         soc:  {soc_mbx: "0x01460200"},
       },
       racl_mappings: {
-        soc: 'top_darjeeling/data/racl/soc_rot_mapping.hjson'
+        soc: 'racl/soc_rot_mapping.hjson'
       }
     },
     { name: "soc_dbg_ctrl",
@@ -1027,7 +1027,7 @@
         num_ranges: 32
       }
       attr: "ipgen",
-      racl_mapping: 'top_darjeeling/data/racl/soc_rot_mapping.hjson'
+      racl_mapping: 'racl/soc_rot_mapping.hjson'
     },
     { name: "rv_core_ibex",
       type: "rv_core_ibex",

diff --git a/util/topgen.py b/util/topgen.py
@@ -586,21 +586,21 @@ def generate_ac_range_check(topcfg: Dict[str, object], out_path: Path) -> None:
 
 # Generate RACL collateral
 def generate_racl(topcfg: Dict[str, object], name_to_block: Dict[str, IpBlock],
-                  out_path: Path) -> None:
+                  hjson_path: Path, out_path: Path) -> None:
     # Not all tops use RACL
     if 'racl_config' not in topcfg:
         return
 
     # Read the top-level RACL information
-    topcfg['racl'] = parse_racl_config(topcfg['racl_config'])
+    topcfg['racl'] = parse_racl_config(hjson_path / topcfg['racl_config'])
 
     # Generate the RACL mappings for all subscribing IPs
     num_subscribing_ips = defaultdict(int)
     for m in topcfg['module']:
         for if_name, mapping_path in m.get('racl_mappings', {}).items():
             parsed_register_mapping, parsed_window_mapping, racl_group, _ = parse_racl_mapping(
                 topcfg['racl'],
-                mapping_path,
+                hjson_path / mapping_path,
                 if_name,
                 name_to_block[m['type']])
             m['racl_mappings'][if_name] = {
@@ -992,7 +992,7 @@ def _process_top(
         generate_rstmgr(completecfg, out_path)
 
     # Generate RACL collateral
-    generate_racl(completecfg, name_to_block, out_path)
+    generate_racl(completecfg, name_to_block, hjson_dir, out_path)
 
     # Generate ac_range_check if there is an instance
     if lib.find_module(completecfg['module'], 'ac_range_check'):