@@ -48,15 +48,20 @@ cirrus_gd5428_vga_device::cirrus_gd5428_vga_device(const machine_config &mconfig
48
48
}
49
49
50
50
cirrus_gd5430_vga_device::cirrus_gd5430_vga_device (const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
51
- : cirrus_gd5428_vga_device (mconfig, CIRRUS_GD5430_VGA, tag, owner, clock)
51
+ : cirrus_gd5430_vga_device (mconfig, CIRRUS_GD5430_VGA, tag, owner, clock)
52
52
{
53
53
m_crtc_space_config = address_space_config (" crtc_regs" , ENDIANNESS_LITTLE, 8 , 8 , 0 , address_map_constructor (FUNC (cirrus_gd5430_vga_device::crtc_map), this ));
54
54
m_gc_space_config = address_space_config (" gc_regs" , ENDIANNESS_LITTLE, 8 , 8 , 0 , address_map_constructor (FUNC (cirrus_gd5430_vga_device::gc_map), this ));
55
55
m_seq_space_config = address_space_config (" sequencer_regs" , ENDIANNESS_LITTLE, 8 , 8 , 0 , address_map_constructor (FUNC (cirrus_gd5430_vga_device::sequencer_map), this ));
56
56
}
57
57
58
+ cirrus_gd5430_vga_device::cirrus_gd5430_vga_device (const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
59
+ : cirrus_gd5428_vga_device(mconfig, type, tag, owner, clock)
60
+ {
61
+ }
62
+
58
63
cirrus_gd5446_vga_device::cirrus_gd5446_vga_device (const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
59
- : cirrus_gd5428_vga_device (mconfig, CIRRUS_GD5446_VGA, tag, owner, clock)
64
+ : cirrus_gd5430_vga_device (mconfig, CIRRUS_GD5446_VGA, tag, owner, clock)
60
65
{
61
66
m_crtc_space_config = address_space_config (" crtc_regs" , ENDIANNESS_LITTLE, 8 , 8 , 0 , address_map_constructor (FUNC (cirrus_gd5446_vga_device::crtc_map), this ));
62
67
m_gc_space_config = address_space_config (" gc_regs" , ENDIANNESS_LITTLE, 8 , 8 , 0 , address_map_constructor (FUNC (cirrus_gd5446_vga_device::gc_map), this ));
@@ -215,8 +220,6 @@ void cirrus_gd5428_vga_device::crtc_map(address_map &map)
215
220
cirrus_define_video_mode ();
216
221
})
217
222
);
218
- // TODO: CR1D for GD543x
219
- // vga.crtc.start_addr_latch = (vga.crtc.start_addr_latch & 0xf7ffff) | ((data & 0x01) << 16);
220
223
map (0x27 , 0x27 ).lr8 (
221
224
NAME ([this ] (offs_t offset) {
222
225
LOGMASKED (LOG_REG, " CR27: Read ID\n " );
@@ -1134,19 +1137,25 @@ uint8_t cirrus_gd5428_vga_device::vga_latch_write(int offs, uint8_t data)
1134
1137
return res;
1135
1138
}
1136
1139
1140
+ // 0xa0000-0xa7fff offset 0
1141
+ // 0xa8000-0xaffff offset 1 (if enabled with GRB bit 0)
1142
+ // notice that "offset" in this context doesn't mean pitch like everything else in the
1143
+ // (S)VGA realm but it's really intended as a window bank base here.
1144
+ uint8_t cirrus_gd5428_vga_device::offset_select (offs_t offset)
1145
+ {
1146
+ const uint8_t sa15 = BIT (offset, 15 );
1147
+ return gc_bank[sa15 & BIT (gc_mode_ext, 0 )];
1148
+ }
1149
+
1137
1150
uint8_t cirrus_gd5428_vga_device::mem_r (offs_t offset)
1138
1151
{
1139
1152
uint32_t addr;
1140
- uint8_t bank;
1141
1153
uint8_t cur_mode = pc_vga_choosevideomode ();
1142
1154
1143
1155
if (gc_locked || offset >= 0x10000 || cur_mode == TEXT_MODE || cur_mode == SCREEN_OFF)
1144
1156
return vga_device::mem_r (offset);
1145
1157
1146
- if (offset >= 0x8000 && offset < 0x10000 && (gc_mode_ext & 0x01 )) // if accessing bank 1 (if enabled)
1147
- bank = gc_bank[1 ];
1148
- else
1149
- bank = gc_bank[0 ];
1158
+ const uint8_t bank = offset_select (offset);
1150
1159
1151
1160
if (gc_mode_ext & 0x20 ) // 16kB bank granularity
1152
1161
addr = bank * 0x4000 ;
@@ -1270,7 +1279,6 @@ uint8_t cirrus_gd5428_vga_device::mem_r(offs_t offset)
1270
1279
void cirrus_gd5428_vga_device::mem_w (offs_t offset, uint8_t data)
1271
1280
{
1272
1281
uint32_t addr;
1273
- uint8_t bank;
1274
1282
uint8_t cur_mode = pc_vga_choosevideomode ();
1275
1283
1276
1284
if (m_blt_system_transfer)
@@ -1302,10 +1310,7 @@ void cirrus_gd5428_vga_device::mem_w(offs_t offset, uint8_t data)
1302
1310
return ;
1303
1311
}
1304
1312
1305
- if (offset >= 0x8000 && offset < 0x10000 && (gc_mode_ext & 0x01 )) // if accessing bank 1 (if enabled)
1306
- bank = gc_bank[1 ];
1307
- else
1308
- bank = gc_bank[0 ];
1313
+ const uint8_t bank = offset_select (offset);
1309
1314
1310
1315
if (gc_mode_ext & 0x20 ) // 16kB bank granularity
1311
1316
addr = bank * 0x4000 ;
@@ -1451,3 +1456,52 @@ void cirrus_gd5428_vga_device::mem_w(offs_t offset, uint8_t data)
1451
1456
}
1452
1457
}
1453
1458
}
1459
+
1460
+ /*
1461
+ * CL-GD5430 overrides
1462
+ */
1463
+
1464
+ void cirrus_gd5430_vga_device::crtc_map (address_map &map)
1465
+ {
1466
+ cirrus_gd5428_vga_device::crtc_map (map);
1467
+ map (0x1d , 0x1d ).lrw8 (
1468
+ NAME ([this ] (offs_t offset) {
1469
+ return m_cr1d;
1470
+ }),
1471
+ NAME ([this ] (offs_t offset, u8 data) {
1472
+ LOGMASKED (LOG_REG, " CR1D: Overlay Extended Control %02x\n " , data);
1473
+ m_cr1d = data;
1474
+ // TODO: '34/'36 onward
1475
+ vga.crtc .start_addr_latch = (vga.crtc .start_addr_latch & 0xf7ffff ) | (BIT (data, 7 ) << 19 );
1476
+ })
1477
+ );
1478
+ }
1479
+
1480
+ void cirrus_gd5430_vga_device::gc_map (address_map &map)
1481
+ {
1482
+ cirrus_gd5428_vga_device::gc_map (map);
1483
+ }
1484
+
1485
+ void cirrus_gd5430_vga_device::sequencer_map (address_map &map)
1486
+ {
1487
+ cirrus_gd5428_vga_device::sequencer_map (map);
1488
+ }
1489
+
1490
+ /*
1491
+ * CL-GD5446 overrides
1492
+ */
1493
+
1494
+ void cirrus_gd5446_vga_device::crtc_map (address_map &map)
1495
+ {
1496
+ cirrus_gd5430_vga_device::crtc_map (map);
1497
+ }
1498
+
1499
+ void cirrus_gd5446_vga_device::gc_map (address_map &map)
1500
+ {
1501
+ cirrus_gd5430_vga_device::gc_map (map);
1502
+ }
1503
+
1504
+ void cirrus_gd5446_vga_device::sequencer_map (address_map &map)
1505
+ {
1506
+ cirrus_gd5430_vga_device::sequencer_map (map);
1507
+ }
0 commit comments