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fix decoding of control registers
1 parent 327ec67 commit 490608c

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2 files changed

+124
-60
lines changed

2 files changed

+124
-60
lines changed

‎src/devices/cpu/tlcs900/dasm900.cpp

Lines changed: 118 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -1519,6 +1519,115 @@ u32 tlcs900_disassembler::opcode_alignment() const
15191519
return 1;
15201520
}
15211521

1522+
void tlcs900_disassembler::decode_control_register_8(std::ostream &stream, uint32_t imm){
1523+
switch( imm )
1524+
{
1525+
case 0x22: util::stream_format(stream, " DMAM0"); break;
1526+
case 0x26: util::stream_format(stream, " DMAM1"); break;
1527+
case 0x2a: util::stream_format(stream, " DMAM2"); break;
1528+
case 0x2e: util::stream_format(stream, " DMAM3"); break;
1529+
default:
1530+
util::stream_format(stream, " unknown (encoding is 0x%02x)", imm);
1531+
break;
1532+
}
1533+
}
1534+
1535+
1536+
void tmp94c241_disassembler::decode_control_register_8(std::ostream &stream, uint32_t imm){
1537+
switch( imm )
1538+
{
1539+
case 0x42: util::stream_format(stream, " DMAM0"); break;
1540+
case 0x46: util::stream_format(stream, " DMAM1"); break;
1541+
case 0x4a: util::stream_format(stream, " DMAM2"); break;
1542+
case 0x4e: util::stream_format(stream, " DMAM3"); break;
1543+
case 0x52: util::stream_format(stream, " DMAM4"); break;
1544+
case 0x56: util::stream_format(stream, " DMAM5"); break;
1545+
case 0x5a: util::stream_format(stream, " DMAM6"); break;
1546+
case 0x5e: util::stream_format(stream, " DMAM7"); break;
1547+
default:
1548+
util::stream_format(stream, " unknown (encoding is 0x%02x)", imm);
1549+
break;
1550+
}
1551+
}
1552+
1553+
1554+
void tlcs900_disassembler::decode_control_register_16(std::ostream &stream, uint32_t imm){
1555+
switch( imm )
1556+
{
1557+
case 0x20: util::stream_format(stream, " DMAC0"); break;
1558+
case 0x24: util::stream_format(stream, " DMAC1"); break;
1559+
case 0x28: util::stream_format(stream, " DMAC2"); break;
1560+
case 0x2c: util::stream_format(stream, " DMAC3"); break;
1561+
case 0x7c: util::stream_format(stream, " NSP"); break;
1562+
default:
1563+
util::stream_format(stream, " unknown (encoding is 0x%02x)", imm);
1564+
break;
1565+
}
1566+
}
1567+
1568+
1569+
void tmp94c241_disassembler::decode_control_register_16(std::ostream &stream, uint32_t imm){
1570+
switch( imm )
1571+
{
1572+
case 0x40: util::stream_format(stream, " DMAC0"); break;
1573+
case 0x44: util::stream_format(stream, " DMAC1"); break;
1574+
case 0x48: util::stream_format(stream, " DMAC2"); break;
1575+
case 0x4c: util::stream_format(stream, " DMAC3"); break;
1576+
case 0x50: util::stream_format(stream, " DMAC4"); break;
1577+
case 0x54: util::stream_format(stream, " DMAC5"); break;
1578+
case 0x58: util::stream_format(stream, " DMAC6"); break;
1579+
case 0x5c: util::stream_format(stream, " DMAC7"); break;
1580+
default:
1581+
util::stream_format(stream, " unknown (encoding is 0x%02x)", imm);
1582+
break;
1583+
}
1584+
}
1585+
1586+
1587+
void tlcs900_disassembler::decode_control_register_32(std::ostream &stream, uint32_t imm){
1588+
switch( imm )
1589+
{
1590+
case 0x00: util::stream_format(stream, " DMAS0"); break;
1591+
case 0x04: util::stream_format(stream, " DMAS1"); break;
1592+
case 0x08: util::stream_format(stream, " DMAS2"); break;
1593+
case 0x0c: util::stream_format(stream, " DMAS3"); break;
1594+
case 0x10: util::stream_format(stream, " DMAD0"); break;
1595+
case 0x14: util::stream_format(stream, " DMAD1"); break;
1596+
case 0x18: util::stream_format(stream, " DMAD2"); break;
1597+
case 0x1c: util::stream_format(stream, " DMAD3"); break;
1598+
default:
1599+
util::stream_format(stream, " unknown (encoding is 0x%02x)", imm);
1600+
break;
1601+
}
1602+
}
1603+
1604+
1605+
void tmp94c241_disassembler::decode_control_register_32(std::ostream &stream, uint32_t imm){
1606+
switch( imm )
1607+
{
1608+
case 0x00: util::stream_format(stream, " DMAS0"); break;
1609+
case 0x04: util::stream_format(stream, " DMAS1"); break;
1610+
case 0x08: util::stream_format(stream, " DMAS2"); break;
1611+
case 0x0c: util::stream_format(stream, " DMAS3"); break;
1612+
case 0x10: util::stream_format(stream, " DMAS4"); break;
1613+
case 0x14: util::stream_format(stream, " DMAS5"); break;
1614+
case 0x18: util::stream_format(stream, " DMAS6"); break;
1615+
case 0x1c: util::stream_format(stream, " DMAS7"); break;
1616+
case 0x20: util::stream_format(stream, " DMAD0"); break;
1617+
case 0x24: util::stream_format(stream, " DMAD1"); break;
1618+
case 0x28: util::stream_format(stream, " DMAD2"); break;
1619+
case 0x2c: util::stream_format(stream, " DMAD3"); break;
1620+
case 0x30: util::stream_format(stream, " DMAD4"); break;
1621+
case 0x34: util::stream_format(stream, " DMAD5"); break;
1622+
case 0x38: util::stream_format(stream, " DMAD6"); break;
1623+
case 0x3c: util::stream_format(stream, " DMAD7"); break;
1624+
default:
1625+
util::stream_format(stream, " unknown (encoding is 0x%02x)", imm);
1626+
break;
1627+
}
1628+
}
1629+
1630+
15221631
offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const data_buffer &opcodes, const data_buffer &params)
15231632
{
15241633
const tlcs900inst *dasm;
@@ -2048,44 +2157,17 @@ offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const
20482157

20492158
case O_CR8:
20502159
imm = opcodes.r8( pos++ );
2051-
switch(imm & 0xe3)
2052-
{
2053-
case 0x42:
2054-
util::stream_format(stream, " DMAM%d", (imm >> 2) & 7);
2055-
break;
2056-
default:
2057-
util::stream_format(stream, " <Unknown 8-bit ControlReg 0x%02X>", imm);
2058-
break;
2059-
}
2160+
decode_control_register_8(stream, imm);
20602161
break;
20612162

20622163
case O_CR16:
20632164
imm = opcodes.r8( pos++ );
2064-
switch(imm & 0xe3)
2065-
{
2066-
case 0x40:
2067-
util::stream_format(stream, " DMAC%d", (imm >> 2) & 7);
2068-
break;
2069-
default:
2070-
util::stream_format(stream, " <Unknown 16-bit ControlReg 0x%02X>", imm);
2071-
break;
2072-
}
2165+
decode_control_register_16(stream, imm);
20732166
break;
20742167

20752168
case O_CR32:
20762169
imm = opcodes.r8( pos++ );
2077-
switch( imm & 0xe3 )
2078-
{
2079-
case 0x00:
2080-
util::stream_format(stream, " DMAS%d", (imm >> 2) & 7);
2081-
break;
2082-
case 0x20:
2083-
util::stream_format(stream, " DMAD%d", (imm >> 2) & 7);
2084-
break;
2085-
default:
2086-
util::stream_format(stream, " <Unknown 32-bit ControlReg 0x%02X>", imm);
2087-
break;
2088-
}
2170+
decode_control_register_32(stream, imm);
20892171
break;
20902172

20912173
case O_D8:
@@ -2216,44 +2298,20 @@ offs_t tlcs900_disassembler::disassemble(std::ostream &stream, offs_t pc, const
22162298

22172299
case O_CR8:
22182300
imm = opcodes.r8( pos++ );
2219-
switch( imm & 0xe3 )
2220-
{
2221-
case 0x42:
2222-
util::stream_format(stream, ",DMAM%d", (imm >> 2) & 7);
2223-
break;
2224-
default:
2225-
util::stream_format(stream, ",<Unknown 8-bit ControlReg 0x%02X>", imm);
2226-
break;
2227-
}
2301+
util::stream_format(stream, ",");
2302+
decode_control_register_8(stream, imm);
22282303
break;
22292304

22302305
case O_CR16:
22312306
imm = opcodes.r8( pos++ );
2232-
switch( imm & 0xe3 )
2233-
{
2234-
case 0x40:
2235-
util::stream_format(stream, ",DMAC%d", (imm >> 2) & 7);
2236-
break;
2237-
default:
2238-
util::stream_format(stream, ",<Unknown 16-bit ControlReg 0x%02X>", imm);
2239-
break;
2240-
}
2307+
util::stream_format(stream, ",");
2308+
decode_control_register_16(stream, imm);
22412309
break;
22422310

22432311
case O_CR32:
22442312
imm = opcodes.r8( pos++ );
2245-
switch( imm & 0xe3 )
2246-
{
2247-
case 0x00:
2248-
util::stream_format(stream, ",DMAS%d", (imm >> 2) & 7);
2249-
break;
2250-
case 0x20:
2251-
util::stream_format(stream, ",DMAD%d", (imm >> 2) & 7);
2252-
break;
2253-
default:
2254-
util::stream_format(stream, ",<Unknown 32-bit ControlReg 0x%02X>", imm);
2255-
break;
2256-
}
2313+
util::stream_format(stream, ",");
2314+
decode_control_register_32(stream, imm);
22572315
break;
22582316

22592317
case O_D8:

‎src/devices/cpu/tlcs900/dasm900.h

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,9 @@ class tlcs900_disassembler : public util::disasm_interface
1515
{
1616
protected:
1717
tlcs900_disassembler(uint16_t num_sfr, const char *const sfr_names[]);
18+
void decode_control_register_8(std::ostream &stream, uint32_t imm);
19+
void decode_control_register_16(std::ostream &stream, uint32_t imm);
20+
void decode_control_register_32(std::ostream &stream, uint32_t imm);
1821

1922
public:
2023
virtual ~tlcs900_disassembler() = default;
@@ -117,6 +120,9 @@ class tmp94c241_disassembler : public tlcs900_disassembler
117120
{
118121
public:
119122
tmp94c241_disassembler();
123+
void decode_control_register_8(std::ostream &stream, uint32_t imm);
124+
void decode_control_register_16(std::ostream &stream, uint32_t imm);
125+
void decode_control_register_32(std::ostream &stream, uint32_t imm);
120126

121127
private:
122128
static const char *const s_sfr_names[];

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