konami/konamigv.cpp, konami/konamigq.cpp, konami/twinkle.cpp: Process SCSI DMA transfers instantaneously. (#12375)

987123879113 · web-flow · commit 698b634196ff · 2024-05-19T04:00:12.000+10:00
* Avoids issues described in MT08860.
* Also added TODO notes about implementing correct DMA timings.
diff --git a/src/mame/konami/konamigq.cpp b/src/mame/konami/konamigq.cpp
@@ -287,7 +287,7 @@ void konamigq_state::scsi_dma_read( uint32_t *p_n_psxram, uint32_t n_address, in
 	m_dma_offset = n_address;
 	m_dma_size = n_size * 4;
 	m_dma_is_write = false;
-	m_dma_timer->adjust(attotime::from_usec(10));
+	m_dma_timer->adjust(attotime::zero);
 }
 
 void konamigq_state::scsi_dma_write( uint32_t *p_n_psxram, uint32_t n_address, int32_t n_size )
@@ -296,12 +296,13 @@ void konamigq_state::scsi_dma_write( uint32_t *p_n_psxram, uint32_t n_address, i
 	m_dma_offset = n_address;
 	m_dma_size = n_size * 4;
 	m_dma_is_write = true;
-	m_dma_timer->adjust(attotime::from_usec(10));
+	m_dma_timer->adjust(attotime::zero);
 }
 
 TIMER_CALLBACK_MEMBER(konamigq_state::scsi_dma_transfer)
 {
-	if (m_dma_requested && m_dma_data_ptr != nullptr && m_dma_size > 0)
+	// TODO: Figure out proper DMA timings
+	while (m_dma_requested && m_dma_data_ptr != nullptr && m_dma_size > 0)
 	{
 		if (m_dma_is_write)
 			m_ncr53cf96->dma_w(util::little_endian_cast<const uint8_t>(m_dma_data_ptr)[m_dma_offset]);
@@ -311,15 +312,12 @@ TIMER_CALLBACK_MEMBER(konamigq_state::scsi_dma_transfer)
 		m_dma_offset++;
 		m_dma_size--;
 	}
-
-	if (m_dma_requested && m_dma_size > 0)
-		m_dma_timer->adjust(attotime::from_usec(10));
 }
 
 void konamigq_state::scsi_drq(int state)
 {
 	if (!m_dma_requested && state)
-		m_dma_timer->adjust(attotime::from_usec(10));
+		m_dma_timer->adjust(attotime::zero);
 
 	m_dma_requested = state;
 }
diff --git a/src/mame/konami/konamigv.cpp b/src/mame/konami/konamigv.cpp
@@ -455,7 +455,7 @@ void konamigv_state::scsi_dma_read(uint32_t *p_n_psxram, uint32_t n_address, int
 	m_dma_offset = n_address;
 	m_dma_size = n_size * 4;
 	m_dma_is_write = false;
-	m_dma_timer->adjust(attotime::from_usec(10));
+	m_dma_timer->adjust(attotime::zero);
 }
 
 void konamigv_state::scsi_dma_write(uint32_t *p_n_psxram, uint32_t n_address, int32_t n_size)
@@ -464,12 +464,13 @@ void konamigv_state::scsi_dma_write(uint32_t *p_n_psxram, uint32_t n_address, in
 	m_dma_offset = n_address;
 	m_dma_size = n_size * 4;
 	m_dma_is_write = true;
-	m_dma_timer->adjust(attotime::from_usec(10));
+	m_dma_timer->adjust(attotime::zero);
 }
 
 TIMER_CALLBACK_MEMBER(konamigv_state::scsi_dma_transfer)
 {
-	if (m_dma_requested && m_dma_data_ptr != nullptr && m_dma_size > 0)
+	// TODO: Figure out proper DMA timings
+	while (m_dma_requested && m_dma_data_ptr != nullptr && m_dma_size > 0)
 	{
 		if (m_dma_is_write)
 			m_ncr53cf96->dma_w(util::little_endian_cast<const uint8_t>(m_dma_data_ptr)[m_dma_offset]);
@@ -479,15 +480,12 @@ TIMER_CALLBACK_MEMBER(konamigv_state::scsi_dma_transfer)
 		m_dma_offset++;
 		m_dma_size--;
 	}
-
-	if (m_dma_requested && m_dma_size > 0)
-		m_dma_timer->adjust(attotime::from_usec(10));
 }
 
 void konamigv_state::scsi_drq(int state)
 {
 	if (!m_dma_requested && state)
-		m_dma_timer->adjust(attotime::from_usec(10));
+		m_dma_timer->adjust(attotime::zero);
 
 	m_dma_requested = state;
 }
diff --git a/src/mame/konami/twinkle.cpp b/src/mame/konami/twinkle.cpp
@@ -1088,7 +1088,7 @@ void twinkle_state::scsi_dma_read(uint32_t *p_n_psxram, uint32_t n_address, int3
 	m_dma_offset = n_address;
 	m_dma_size = n_size * 4;
 	m_dma_is_write = false;
-	m_dma_timer->adjust(attotime::from_usec(10));
+	m_dma_timer->adjust(attotime::zero);
 }
 
 void twinkle_state::scsi_dma_write(uint32_t *p_n_psxram, uint32_t n_address, int32_t n_size)
@@ -1097,12 +1097,13 @@ void twinkle_state::scsi_dma_write(uint32_t *p_n_psxram, uint32_t n_address, int
 	m_dma_offset = n_address;
 	m_dma_size = n_size * 4;
 	m_dma_is_write = true;
-	m_dma_timer->adjust(attotime::from_usec(10));
+	m_dma_timer->adjust(attotime::zero);
 }
 
 TIMER_CALLBACK_MEMBER(twinkle_state::scsi_dma_transfer)
 {
-	if (m_dma_requested && m_dma_data_ptr != nullptr && m_dma_size > 0)
+	// TODO: Figure out proper DMA timings
+	while (m_dma_requested && m_dma_data_ptr != nullptr && m_dma_size > 0)
 	{
 		if (m_dma_is_write)
 			m_ncr53cf96->dma_w(util::little_endian_cast<const uint8_t>(m_dma_data_ptr)[m_dma_offset]);
@@ -1112,15 +1113,12 @@ TIMER_CALLBACK_MEMBER(twinkle_state::scsi_dma_transfer)
 		m_dma_offset++;
 		m_dma_size--;
 	}
-
-	if (m_dma_requested && m_dma_size > 0)
-		m_dma_timer->adjust(attotime::from_usec(10));
 }
 
 void twinkle_state::scsi_drq(int state)
 {
 	if (!m_dma_requested && state)
-		m_dma_timer->adjust(attotime::from_usec(10));
+		m_dma_timer->adjust(attotime::zero);
 
 	m_dma_requested = state;
 }

Original file line number	Diff line number	Diff line change
`@@ -287,7 +287,7 @@ void konamigq_state::scsi_dma_read( uint32_t *p_n_psxram, uint32_t n_address, in`
`287`	`287`	`m_dma_offset = n_address;`
`288`	`288`	`m_dma_size = n_size * 4;`
`289`	`289`	`m_dma_is_write = false;`
`290`		`- m_dma_timer->adjust(attotime::from_usec(10));`
	`290`	`+ m_dma_timer->adjust(attotime::zero);`
`291`	`291`	`}`
`292`	`292`
`293`	`293`	`void konamigq_state::scsi_dma_write( uint32_t *p_n_psxram, uint32_t n_address, int32_t n_size )`
`@@ -296,12 +296,13 @@ void konamigq_state::scsi_dma_write( uint32_t *p_n_psxram, uint32_t n_address, i`
`296`	`296`	`m_dma_offset = n_address;`
`297`	`297`	`m_dma_size = n_size * 4;`
`298`	`298`	`m_dma_is_write = true;`
`299`		`- m_dma_timer->adjust(attotime::from_usec(10));`
	`299`	`+ m_dma_timer->adjust(attotime::zero);`
`300`	`300`	`}`
`301`	`301`
`302`	`302`	`TIMER_CALLBACK_MEMBER(konamigq_state::scsi_dma_transfer)`
`303`	`303`	`{`
`304`		`- if (m_dma_requested && m_dma_data_ptr != nullptr && m_dma_size > 0)`
	`304`	`+ // TODO: Figure out proper DMA timings`
	`305`	`+ while (m_dma_requested && m_dma_data_ptr != nullptr && m_dma_size > 0)`
`305`	`306`	`{`
`306`	`307`	`if (m_dma_is_write)`
`307`	`308`	`m_ncr53cf96->dma_w(util::little_endian_cast<const uint8_t>(m_dma_data_ptr)[m_dma_offset]);`
`@@ -311,15 +312,12 @@ TIMER_CALLBACK_MEMBER(konamigq_state::scsi_dma_transfer)`
`311`	`312`	`m_dma_offset++;`
`312`	`313`	`m_dma_size--;`
`313`	`314`	`}`
`314`		`-`
`315`		`- if (m_dma_requested && m_dma_size > 0)`
`316`		`- m_dma_timer->adjust(attotime::from_usec(10));`
`317`	`315`	`}`
`318`	`316`
`319`	`317`	`void konamigq_state::scsi_drq(int state)`
`320`	`318`	`{`
`321`	`319`	`if (!m_dma_requested && state)`
`322`		`- m_dma_timer->adjust(attotime::from_usec(10));`
	`320`	`+ m_dma_timer->adjust(attotime::zero);`
`323`	`321`
`324`	`322`	`m_dma_requested = state;`
`325`	`323`	`}`
Original file line number	Diff line number	Diff line change
`@@ -455,7 +455,7 @@ void konamigv_state::scsi_dma_read(uint32_t *p_n_psxram, uint32_t n_address, int`
`455`	`455`	`m_dma_offset = n_address;`
`456`	`456`	`m_dma_size = n_size * 4;`
`457`	`457`	`m_dma_is_write = false;`
`458`		`- m_dma_timer->adjust(attotime::from_usec(10));`
	`458`	`+ m_dma_timer->adjust(attotime::zero);`
`459`	`459`	`}`
`460`	`460`
`461`	`461`	`void konamigv_state::scsi_dma_write(uint32_t *p_n_psxram, uint32_t n_address, int32_t n_size)`
`@@ -464,12 +464,13 @@ void konamigv_state::scsi_dma_write(uint32_t *p_n_psxram, uint32_t n_address, in`
`464`	`464`	`m_dma_offset = n_address;`
`465`	`465`	`m_dma_size = n_size * 4;`
`466`	`466`	`m_dma_is_write = true;`
`467`		`- m_dma_timer->adjust(attotime::from_usec(10));`
	`467`	`+ m_dma_timer->adjust(attotime::zero);`
`468`	`468`	`}`
`469`	`469`
`470`	`470`	`TIMER_CALLBACK_MEMBER(konamigv_state::scsi_dma_transfer)`
`471`	`471`	`{`
`472`		`- if (m_dma_requested && m_dma_data_ptr != nullptr && m_dma_size > 0)`
	`472`	`+ // TODO: Figure out proper DMA timings`
	`473`	`+ while (m_dma_requested && m_dma_data_ptr != nullptr && m_dma_size > 0)`
`473`	`474`	`{`
`474`	`475`	`if (m_dma_is_write)`
`475`	`476`	`m_ncr53cf96->dma_w(util::little_endian_cast<const uint8_t>(m_dma_data_ptr)[m_dma_offset]);`
`@@ -479,15 +480,12 @@ TIMER_CALLBACK_MEMBER(konamigv_state::scsi_dma_transfer)`
`479`	`480`	`m_dma_offset++;`
`480`	`481`	`m_dma_size--;`
`481`	`482`	`}`
`482`		`-`
`483`		`- if (m_dma_requested && m_dma_size > 0)`
`484`		`- m_dma_timer->adjust(attotime::from_usec(10));`
`485`	`483`	`}`
`486`	`484`
`487`	`485`	`void konamigv_state::scsi_drq(int state)`
`488`	`486`	`{`
`489`	`487`	`if (!m_dma_requested && state)`
`490`		`- m_dma_timer->adjust(attotime::from_usec(10));`
	`488`	`+ m_dma_timer->adjust(attotime::zero);`
`491`	`489`
`492`	`490`	`m_dma_requested = state;`
`493`	`491`	`}`
Original file line number	Diff line number	Diff line change
`@@ -1088,7 +1088,7 @@ void twinkle_state::scsi_dma_read(uint32_t *p_n_psxram, uint32_t n_address, int3`
`1088`	`1088`	`m_dma_offset = n_address;`
`1089`	`1089`	`m_dma_size = n_size * 4;`
`1090`	`1090`	`m_dma_is_write = false;`
`1091`		`- m_dma_timer->adjust(attotime::from_usec(10));`
	`1091`	`+ m_dma_timer->adjust(attotime::zero);`
`1092`	`1092`	`}`
`1093`	`1093`
`1094`	`1094`	`void twinkle_state::scsi_dma_write(uint32_t *p_n_psxram, uint32_t n_address, int32_t n_size)`
`@@ -1097,12 +1097,13 @@ void twinkle_state::scsi_dma_write(uint32_t *p_n_psxram, uint32_t n_address, int`
`1097`	`1097`	`m_dma_offset = n_address;`
`1098`	`1098`	`m_dma_size = n_size * 4;`
`1099`	`1099`	`m_dma_is_write = true;`
`1100`		`- m_dma_timer->adjust(attotime::from_usec(10));`
	`1100`	`+ m_dma_timer->adjust(attotime::zero);`
`1101`	`1101`	`}`
`1102`	`1102`
`1103`	`1103`	`TIMER_CALLBACK_MEMBER(twinkle_state::scsi_dma_transfer)`
`1104`	`1104`	`{`
`1105`		`- if (m_dma_requested && m_dma_data_ptr != nullptr && m_dma_size > 0)`
	`1105`	`+ // TODO: Figure out proper DMA timings`
	`1106`	`+ while (m_dma_requested && m_dma_data_ptr != nullptr && m_dma_size > 0)`
`1106`	`1107`	`{`
`1107`	`1108`	`if (m_dma_is_write)`
`1108`	`1109`	`m_ncr53cf96->dma_w(util::little_endian_cast<const uint8_t>(m_dma_data_ptr)[m_dma_offset]);`
`@@ -1112,15 +1113,12 @@ TIMER_CALLBACK_MEMBER(twinkle_state::scsi_dma_transfer)`
`1112`	`1113`	`m_dma_offset++;`
`1113`	`1114`	`m_dma_size--;`
`1114`	`1115`	`}`
`1115`		`-`
`1116`		`- if (m_dma_requested && m_dma_size > 0)`
`1117`		`- m_dma_timer->adjust(attotime::from_usec(10));`
`1118`	`1116`	`}`
`1119`	`1117`
`1120`	`1118`	`void twinkle_state::scsi_drq(int state)`
`1121`	`1119`	`{`
`1122`	`1120`	`if (!m_dma_requested && state)`
`1123`		`- m_dma_timer->adjust(attotime::from_usec(10));`
	`1121`	`+ m_dma_timer->adjust(attotime::zero);`
`1124`	`1122`
`1125`	`1123`	`m_dma_requested = state;`
`1126`	`1124`	`}`